[v2,46/48] ARM: tegra: ventana: Enable core voltage scaling

Message ID	20201217180638.22748-47-digetx@gmail.com
State	New
Headers	show Return-Path: <linux-media-owner@kernel.org> From: Dmitry Osipenko <digetx@gmail.com> To: Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Mark Brown <broonie@kernel.org>, Liam Girdwood <lgirdwood@gmail.com>, Ulf Hansson <ulf.hansson@linaro.org>, Mauro Carvalho Chehab <mchehab@kernel.org>, Rob Herring <robh+dt@kernel.org>, Peter Geis <pgwipeout@gmail.com>, Nicolas Chauvet <kwizart@gmail.com>, Krzysztof Kozlowski <krzk@kernel.org>, "Rafael J. Wysocki" <rjw@rjwysocki.net>, Kevin Hilman <khilman@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, Viresh Kumar <vireshk@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com> Cc: devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 46/48] ARM: tegra: ventana: Enable core voltage scaling Date: Thu, 17 Dec 2020 21:06:36 +0300 Message-Id: <20201217180638.22748-47-digetx@gmail.com> In-Reply-To: <20201217180638.22748-1-digetx@gmail.com> References: <20201217180638.22748-1-digetx@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs \| expand [v2,00/48] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs [v2,01/48] dt-bindings: memory: tegra20: emc: Replace core regulator with power domain [v2,02/48] dt-bindings: memory: tegra30: emc: Replace core regulator with power domain [v2,03/48] dt-bindings: memory: tegra124: emc: Replace core regulator with power domain [v2,04/48] dt-bindings: host1x: Document OPP and power domain properties [v2,05/48] media: dt: bindings: tegra-vde: Document OPP and power domain properties [v2,06/48] dt-bindings: clock: tegra: Document clocks sub-node [v2,07/48] dt-bindings: arm: tegra: Add binding for core power domain [v2,08/48] regulator: Make regulator_sync_voltage() usable by coupled regulators [v2,09/48] opp: Add dev_pm_opp_sync_regulators() [v2,10/48] opp: Add dev_pm_opp_set_voltage() [v2,11/48] opp: Add dev_pm_opp_find_level_ceil() [v2,12/48] opp: Add dev_pm_opp_get_required_pstate() [v2,13/48] opp: Add resource-managed versions of OPP API functions [v2,14/48] opp: Filter out OPPs based on availability of a required-OPP [v2,15/48] opp: Support set_opp() customization without requiring to use regulators [v2,16/48] opp: Handle missing OPP table in dev_pm_opp_xlate_performance_state() [v2,17/48] opp: Correct debug message in _opp_add_static_v2() [v2,18/48] opp: Print OPP level in debug message of _opp_add_static_v2() [v2,19/48] opp: Fix adding OPP entries in a wrong order if rate is unavailable [v2,20/48] PM: domains: Make set_performance_state() callback optional [v2,21/48] PM: domains: Add "performance" column to debug summary [v2,22/48] soc/tegra: pmc: Fix imbalanced clock disabling in error code path [v2,23/48] soc/tegra: pmc: Pulse resets after removing power clamp [v2,24/48] soc/tegra: pmc: Ensure that clock rates aren't too high [v2,25/48] soc/tegra: pmc: Print out domain name when reset fails to acquire [v2,26/48] soc/tegra: Add devm_tegra_core_dev_init_opp_table() [v2,27/48] soc/tegra: Add CONFIG_SOC_TEGRA_COMMON and select PM_OPP by default [v2,28/48] soc/tegra: Introduce core power domain driver [v2,29/48] soc/tegra: pmc: Link domains to the parent Core domain [v2,30/48] soc/tegra: regulators: Fix locking up when voltage-spread is out of range [v2,31/48] soc/tegra: regulators: Support Core domain state syncing [v2,32/48] clk: tegra: Support runtime PM, power domain and OPP [v2,33/48] gpu: host1x: Add host1x_channel_stop() [v2,34/48] gpu: host1x: Support power management [v2,35/48] drm/tegra: dc: Support OPP and SoC core voltage scaling [v2,36/48] drm/tegra: gr2d: Correct swapped device-tree compatibles [v2,37/48] drm/tegra: gr2d: Support OPP and power management [v2,38/48] drm/tegra: g3d: Support OPP and power management [v2,39/48] drm/tegra: vic: Stop channel before suspending [v2,40/48] media: staging: tegra-vde: Support OPP and generic power domain [v2,41/48] memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table() [v2,42/48] memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table() [v2,43/48] ARM: tegra: Add OPP tables and power domains to Tegra20 device-tree [v2,44/48] ARM: tegra: Add OPP tables and power domains to Tegra30 device-tree [v2,45/48] ARM: tegra: acer-a500: Enable core voltage scaling [v2,46/48] ARM: tegra: ventana: Enable core voltage scaling [v2,47/48] ARM: tegra: ventana: Support CPU voltage scaling and thermal throttling [v2,48/48] ARM: tegra: cardhu: Support CPU voltage scaling and thermal throttling

Message ID

20201217180638.22748-47-digetx@gmail.com

State

New

Headers

From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>, Mark Brown <broonie@kernel.org>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Rob Herring <robh+dt@kernel.org>, Peter Geis <pgwipeout@gmail.com>,
	Nicolas Chauvet <kwizart@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Kevin Hilman <khilman@kernel.org>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Viresh Kumar <vireshk@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>
Cc: devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-media@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: [PATCH v2 46/48] ARM: tegra: ventana: Enable core voltage scaling
Date: Thu, 17 Dec 2020 21:06:36 +0300
Message-Id: <20201217180638.22748-47-digetx@gmail.com>
In-Reply-To: <20201217180638.22748-1-digetx@gmail.com>
References: <20201217180638.22748-1-digetx@gmail.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs | expand

Commit Message

Dmitry Osipenko Dec. 17, 2020, 6:06 p.m. UTC

Allow lower core voltages on Ventana board.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/boot/dts/tegra20-ventana.dts | 32 ++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 0b03b3b0fd0c..14ace2ef749c 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -422,16 +422,26 @@  sys_reg: sys {
 
 				vdd_core: sm0 {
 					regulator-name = "vdd_sm0,vdd_core";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
+					regulator-coupled-max-spread = <170000 550000>;
 					regulator-always-on;
+					regulator-boot-on;
+
+					nvidia,tegra-core-regulator;
 				};
 
-				sm1 {
+				vdd_cpu: sm1 {
 					regulator-name = "vdd_sm1,vdd_cpu";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
+					regulator-min-microvolt = <750000>;
+					regulator-max-microvolt = <1125000>;
+					regulator-coupled-with = <&vdd_core &rtc_vdd>;
+					regulator-coupled-max-spread = <550000 550000>;
 					regulator-always-on;
+					regulator-boot-on;
+
+					nvidia,tegra-cpu-regulator;
 				};
 
 				sm2_reg: sm2 {
@@ -450,10 +460,16 @@  ldo1 {
 					regulator-always-on;
 				};
 
-				ldo2 {
+				rtc_vdd: ldo2 {
 					regulator-name = "vdd_ldo2,vdd_rtc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&vdd_core &vdd_cpu>;
+					regulator-coupled-max-spread = <170000 550000>;
+					regulator-always-on;
+					regulator-boot-on;
+
+					nvidia,tegra-rtc-regulator;
 				};
 
 				ldo3 {

[v2,46/48] ARM: tegra: ventana: Enable core voltage scaling

Commit Message

Patch