@@ -1264,17 +1264,15 @@
)
(define_insn "*combine_vcvtf2i"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
+ [(set (match_operand:SI 0 "s_register_operand" "=t")
+ (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "0")
(match_operand 2
"const_double_vcvt_power_of_two" "Dp")))))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
- "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1"
+ "vcvt%?.s32.f32\\t%0, %1, %v2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "ce_count" "2")
- (set_attr "type" "f_cvtf2i")
- (set_attr "length" "8")]
+ (set_attr "type" "f_cvtf2i")]
)
;; Store multiple insn used in function prologue.
Hi, This fixes the issue in PR target/62098 where the pattern is clearly bogus and it's not clear what I was thinking when I ok'd it. The vcvt instruction in this form writes to it's source register and this should have been modelled correctly in the backend in this form rather than the bogus pattern that we managed to generate. Tested cross on arm-none-linux-gnueabihf with no regressions, verified that the testcase from the bug report clearly DTRT. I haven't yet dealt with a testcase but that will follow suit. Applied so far on trunk after cross-testing on armv7-a, neon, float-abi=hard, arm state and will backport to 4.9 after suitable testing there along with the afore mentioned testcase. regards Ramana 2014-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/62098 * config/arm/vfp.md (*combine_vcvtf2i): Fix constraint. Remove unnecessary attributes.