| Message ID | 20201231142948.3241780-7-paul.kocialkowski@bootlin.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Allwinner MIPI CSI-2 support for A31/V3s/A83T | expand |
On Thu, Dec 31, 2020 at 03:29:39PM +0100, Paul Kocialkowski wrote: > The A31 CSI controller supports two distinct input interfaces: > parallel and an external MIPI CSI-2 bridge. The parallel interface > is often connected to a set of hardware pins while the MIPI CSI-2 > bridge is an internal FIFO-ish link. As a result, these two inputs > are distinguished as two different ports. > > Note that only one of the two may be present on a controller instance. > For example, the V3s has one controller dedicated to MIPI-CSI2 and one > dedicated to parallel. > > Update the binding with an explicit ports node that holds two distinct > port nodes: one for parallel input and one for MIPI CSI-2. > > This is backward-compatible with the single-port approach that was > previously taken for representing the parallel interface port, which > stays enumerated as fwnode port 0. > > Note that additional ports may be added in the future, especially to > support feeding the CSI controller's output to the ISP. > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Maxime Ripard <mripard@kernel.org> Maxime
diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml index 1fd9b5532a21..77ded77505e9 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml @@ -67,6 +67,62 @@ properties: additionalProperties: false + ports: + type: object + + properties: + port@0: + type: object + description: Parallel input port, connect to a parallel sensor + + properties: + reg: + const: 0 + + endpoint: + type: object + + properties: + remote-endpoint: true + + bus-width: + enum: [ 8, 10, 12, 16 ] + + pclk-sample: true + hsync-active: true + vsync-active: true + + required: + - bus-width + - remote-endpoint + + required: + - endpoint + + additionalProperties: false + + port@1: + type: object + description: MIPI CSI-2 bridge input port + + properties: + reg: + const: 1 + + endpoint: + type: object + + properties: + remote-endpoint: true + + required: + - remote-endpoint + + required: + - endpoint + + additionalProperties: false + required: - compatible - reg @@ -95,19 +151,25 @@ examples: "ram"; resets = <&ccu RST_BUS_CSI>; - port { - /* Parallel bus endpoint */ - csi1_ep: endpoint { - remote-endpoint = <&adv7611_ep>; - bus-width = <16>; - - /* - * If hsync-active/vsync-active are missing, - * embedded BT.656 sync is used. - */ - hsync-active = <0>; /* Active low */ - vsync-active = <0>; /* Active low */ - pclk-sample = <1>; /* Rising */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + /* Parallel bus endpoint */ + csi1_ep: endpoint { + remote-endpoint = <&adv7611_ep>; + bus-width = <16>; + + /* + * If hsync-active/vsync-active are missing, + * embedded BT.656 sync is used. + */ + hsync-active = <0>; /* Active low */ + vsync-active = <0>; /* Active low */ + pclk-sample = <1>; /* Rising */ + }; }; }; };