| Message ID | 20210105122649.13581-5-manivannan.sadhasivam@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Devicetree update for SDX55 platform | expand |
On 05-01-21, 17:56, Manivannan Sadhasivam wrote: > Add devicetree support for SDHCI controller found in Qualcomm SDX55 SoC. > The SDHCI controller used in this SoC is based on the MSM SDHCI v5 IP. > Hence, the support is added by reusing the existing sdhci driver with > "qcom,sdhci-msm-v5" as the fallback. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm/boot/dts/qcom-sdx55.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi > index eeb6bf392f93..3f8e98bfc020 100644 > --- a/arch/arm/boot/dts/qcom-sdx55.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi > @@ -154,6 +154,18 @@ blsp1_uart3: serial@831000 { > status = "disabled"; > }; > > + sdhc_1: sdhci@8804000 { Any reason why this is sdhc_1 label, do we have another one..? > + compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x08804000 0x1000>; > + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", "pwr_irq"; > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>; > + clock-names = "iface", "core"; > + status = "disabled"; > + }; > + > pdc: interrupt-controller@b210000 { > compatible = "qcom,sdx55-pdc", "qcom,pdc"; > reg = <0x0b210000 0x30000>; > -- > 2.25.1 -- ~Vinod
On Tue, Jan 05, 2021 at 09:22:59PM +0530, Vinod Koul wrote: > On 05-01-21, 17:56, Manivannan Sadhasivam wrote: > > Add devicetree support for SDHCI controller found in Qualcomm SDX55 SoC. > > The SDHCI controller used in this SoC is based on the MSM SDHCI v5 IP. > > Hence, the support is added by reusing the existing sdhci driver with > > "qcom,sdhci-msm-v5" as the fallback. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > arch/arm/boot/dts/qcom-sdx55.dtsi | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi > > index eeb6bf392f93..3f8e98bfc020 100644 > > --- a/arch/arm/boot/dts/qcom-sdx55.dtsi > > +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi > > @@ -154,6 +154,18 @@ blsp1_uart3: serial@831000 { > > status = "disabled"; > > }; > > > > + sdhc_1: sdhci@8804000 { > > Any reason why this is sdhc_1 label, do we have another one..? > The documentation lists this as SDC1 eventhough there seems to be no other instances. Thanks, Mani
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index eeb6bf392f93..3f8e98bfc020 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -154,6 +154,18 @@ blsp1_uart3: serial@831000 { status = "disabled"; }; + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface", "core"; + status = "disabled"; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx55-pdc", "qcom,pdc"; reg = <0x0b210000 0x30000>;
Add devicetree support for SDHCI controller found in Qualcomm SDX55 SoC. The SDHCI controller used in this SoC is based on the MSM SDHCI v5 IP. Hence, the support is added by reusing the existing sdhci driver with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm/boot/dts/qcom-sdx55.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.25.1