| Message ID | 1411568192.28127.40.camel@kazak.uk.xensource.com |
|---|---|
| State | New |
| Headers | show |
Hi Ian, On 09/24/2014 03:16 PM, Ian Campbell wrote: > On Wed, 2014-09-24 at 05:36 -0700, Suriyan Ramasami wrote: > Thanks, > >> (XEN) VTCR_EL2: 80003518 > > THis has changed from 0x80003558 before this change (sorry, this was in > your original report too and I failed to spot it). > > The missing bit changes the starting level of the PT from L1 to L2, > which ain't gonna work very well ;-). > > I can't for the life of me figure out how/why this works on arndale, but > it does... It also works on Midway (without the patch below). I guess it depends on the position of the RAM in the p2m. > Anyway, does this fix it for you? > > 8<------------------ > > From ada27d3a56ba89513721e24abe4a4bebee2ab9cf Mon Sep 17 00:00:00 2001 > From: Ian Campbell <ian.campbell@citrix.com> > Date: Wed, 24 Sep 2014 15:13:28 +0100 > Subject: [PATCH] xen: arm: correct VTCR setting on arm32. > > 1c92a2aaf8c6 "xen: arm: support for up to 48-bit IPA addressing on > arm64" inadvertently changes the VTCR setting for 32-bit from > 0x80003558 to 0x80003518, changing the SL0 setting from 0x1 (p2m > starts at L1) to 0x0 (p2m starts at L2). > > For some (inexplicable) reason this doesn't cause any issue on > Arndale but it does on the OdroidXU. > > Reported-by: Suriyan Ramasami <suriyan.r@gmail.com> > Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Reviewed-by: Julien Grall <julien.grall@linaro.org> Regards,
Hello Ian On Wed, Sep 24, 2014 at 8:58 AM, Julien Grall <julien.grall@linaro.org> wrote: > Hi Ian, > > On 09/24/2014 03:16 PM, Ian Campbell wrote: >> On Wed, 2014-09-24 at 05:36 -0700, Suriyan Ramasami wrote: >> Thanks, >> >>> (XEN) VTCR_EL2: 80003518 >> >> THis has changed from 0x80003558 before this change (sorry, this was in >> your original report too and I failed to spot it). >> >> The missing bit changes the starting level of the PT from L1 to L2, >> which ain't gonna work very well ;-). >> >> I can't for the life of me figure out how/why this works on arndale, but >> it does... > > It also works on Midway (without the patch below). I guess it depends on > the position of the RAM in the p2m. > >> Anyway, does this fix it for you? >> This does indeed fix it for the OdroidXU. (XEN) P2M: 40-bit IPA (XEN) P2M: 3 levels with order-1 root, VTCR 0x80003558 It now boots up fine! Thanks - Suriyan >> 8<------------------ >> >> From ada27d3a56ba89513721e24abe4a4bebee2ab9cf Mon Sep 17 00:00:00 2001 >> From: Ian Campbell <ian.campbell@citrix.com> >> Date: Wed, 24 Sep 2014 15:13:28 +0100 >> Subject: [PATCH] xen: arm: correct VTCR setting on arm32. >> >> 1c92a2aaf8c6 "xen: arm: support for up to 48-bit IPA addressing on >> arm64" inadvertently changes the VTCR setting for 32-bit from >> 0x80003558 to 0x80003518, changing the SL0 setting from 0x1 (p2m >> starts at L1) to 0x0 (p2m starts at L2). >> >> For some (inexplicable) reason this doesn't cause any issue on >> Arndale but it does on the OdroidXU. >> >> Reported-by: Suriyan Ramasami <suriyan.r@gmail.com> >> Signed-off-by: Ian Campbell <ian.campbell@citrix.com> > > Reviewed-by: Julien Grall <julien.grall@linaro.org> > > Regards, > > -- > Julien Grall
On Wed, 2014-09-24 at 09:11 -0700, Suriyan Ramasami wrote: > Hello Ian > > On Wed, Sep 24, 2014 at 8:58 AM, Julien Grall <julien.grall@linaro.org> wrote: > > Hi Ian, > > > > On 09/24/2014 03:16 PM, Ian Campbell wrote: > >> On Wed, 2014-09-24 at 05:36 -0700, Suriyan Ramasami wrote: > >> Thanks, > >> > >>> (XEN) VTCR_EL2: 80003518 > >> > >> THis has changed from 0x80003558 before this change (sorry, this was in > >> your original report too and I failed to spot it). > >> > >> The missing bit changes the starting level of the PT from L1 to L2, > >> which ain't gonna work very well ;-). > >> > >> I can't for the life of me figure out how/why this works on arndale, but > >> it does... > > > > It also works on Midway (without the patch below). I guess it depends on > > the position of the RAM in the p2m. > > > >> Anyway, does this fix it for you? > >> > > This does indeed fix it for the OdroidXU. > (XEN) P2M: 40-bit IPA > (XEN) P2M: 3 levels with order-1 root, VTCR 0x80003558 > > It now boots up fine! Thanks, I shall add your Tested-by: when I commit. Ian.
On Wed, 2014-09-24 at 16:58 +0100, Julien Grall wrote: > Hi Ian, > > On 09/24/2014 03:16 PM, Ian Campbell wrote: > > On Wed, 2014-09-24 at 05:36 -0700, Suriyan Ramasami wrote: > > Thanks, > > > >> (XEN) VTCR_EL2: 80003518 > > > > THis has changed from 0x80003558 before this change (sorry, this was in > > your original report too and I failed to spot it). > > > > The missing bit changes the starting level of the PT from L1 to L2, > > which ain't gonna work very well ;-). > > > > I can't for the life of me figure out how/why this works on arndale, but > > it does... > > It also works on Midway (without the patch below). I guess it depends on > the position of the RAM in the p2m. I was thinking that presenting a three level PT to an MMU which is expecting two levels was unlikely to work, but the interesting properties of the leaf-pte's table bit always being set might mean this would actually work (sort of) if things were suitably aligned as you are implying. I am happy with that theory without digging any further. Ian.
diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 4dccf7b..70929fc 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1163,6 +1163,7 @@ void __init setup_virt_paging(void) #ifdef CONFIG_ARM_32 printk("P2M: 40-bit IPA\n"); val |= VTCR_T0SZ(0x18); /* 40 bit IPA */ + val |= VTCR_SL0(0x1); /* P2M starts at first level */ #else /* CONFIG_ARM_64 */ const struct { unsigned int pabits; /* Physical Address Size */