| Message ID | 1412959792-20708-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
On 10/10/2014 12:49 PM, Peter Maydell wrote: > The DZP bit in the DCZID system register should be set if > the control bits which prohibit use of the DC ZVA instruction > have been set (it stands for Data Zero Prohibited). However > we had the sense of the test inverted; fix this so that the > bit reads correctly. > > To avoid this regressing the behaviour of the user-mode > emulator, we must set the DZE bit in the SCTLR for that > config so that userspace continues to see DZP as zero (it > was getting the correct result by accident previously). > > Reported-by: Christopher Covington <cov@codeaurora.org> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target-arm/cpu.c | 4 ++-- > target-arm/helper.c | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index edfd586..28e2701 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -102,8 +102,8 @@ static void arm_cpu_reset(CPUState *s) > env->aarch64 = 1; > #if defined(CONFIG_USER_ONLY) > env->pstate = PSTATE_MODE_EL0t; > - /* Userspace expects access to CTL_EL0 and the cache ops */ > - env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; > + /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ > + env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; > /* and to the FP/Neon instructions */ > env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); > #else > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 2669e15..904f101 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2018,7 +2018,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) > int dzp_bit = 1 << 4; > > /* DZP indicates whether DC ZVA access is allowed */ > - if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) { > + if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) { > dzp_bit = 0; > } > return cpu->dcz_blocksize | dzp_bit; > Reviewed-by: Christopher Covington <cov@codeaurora.org> Thanks Peter! Christopher
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index edfd586..28e2701 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -102,8 +102,8 @@ static void arm_cpu_reset(CPUState *s) env->aarch64 = 1; #if defined(CONFIG_USER_ONLY) env->pstate = PSTATE_MODE_EL0t; - /* Userspace expects access to CTL_EL0 and the cache ops */ - env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; + /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ + env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; /* and to the FP/Neon instructions */ env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); #else diff --git a/target-arm/helper.c b/target-arm/helper.c index 2669e15..904f101 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2018,7 +2018,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) int dzp_bit = 1 << 4; /* DZP indicates whether DC ZVA access is allowed */ - if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) { + if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) { dzp_bit = 0; } return cpu->dcz_blocksize | dzp_bit;
The DZP bit in the DCZID system register should be set if the control bits which prohibit use of the DC ZVA instruction have been set (it stands for Data Zero Prohibited). However we had the sense of the test inverted; fix this so that the bit reads correctly. To avoid this regressing the behaviour of the user-mode emulator, we must set the DZE bit in the SCTLR for that config so that userspace continues to see DZP as zero (it was getting the correct result by accident previously). Reported-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/cpu.c | 4 ++-- target-arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)