[ARM-AArch64/testsuite,v3,06/21] Add unary saturating operators: vqabs and vqneg.

Message ID	1413896593-26607-7-git-send-email-christophe.lyon@linaro.org
State	New
Headers	show Return-Path: <patchwork-forward+bncBDNJJ5OM3EFRBJVUTGRAKGQEKL3OO6Q@linaro.org> MIME-Version: 1.0 Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::229 as permitted sender) client-ip=2a00:1450:4010:c03::229; Received-SPF: pass (google.com: domain of gcc-patches-return-381272-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list Sender: gcc-patches-owner@gcc.gnu.org From: Christophe Lyon <christophe.lyon@linaro.org> To: gcc-patches@gcc.gnu.org Subject: [Patch ARM-AArch64/testsuite v3 06/21] Add unary saturating operators: vqabs and vqneg. Date: Tue, 21 Oct 2014 15:02:58 +0200 Message-Id: <1413896593-26607-7-git-send-email-christophe.lyon@linaro.org> In-Reply-To: <1413896593-26607-1-git-send-email-christophe.lyon@linaro.org> References: <1413896593-26607-1-git-send-email-christophe.lyon@linaro.org>

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc new file mode 100644 index 0000000..3f6d984 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc @@ -0,0 +1,80 @@ +/* Template file for saturating unary operator validation. + + This file is meant to be included by the relevant test files, which + have to define the intrinsic family to test. If a given intrinsic + supports variants which are not supported by all the other + saturating unary operators, these can be tested by providing a + definition for EXTRA_TESTS. */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* y=OP(x), then store the result. */ +#define TEST_UNARY_SAT_OP1(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \ + Set_Neon_Cumulative_Sat(0); \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \ + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vector_res, T1, W, N)); \ + CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT) + +#define TEST_UNARY_SAT_OP(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \ + TEST_UNARY_SAT_OP1(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) + + /* No need for 64 bits variants. */ + DECL_VARIABLE(vector, int, 8, 8); + DECL_VARIABLE(vector, int, 16, 4); + DECL_VARIABLE(vector, int, 32, 2); + DECL_VARIABLE(vector, int, 8, 16); + DECL_VARIABLE(vector, int, 16, 8); + DECL_VARIABLE(vector, int, 32, 4); + + DECL_VARIABLE(vector_res, int, 8, 8); + DECL_VARIABLE(vector_res, int, 16, 4); + DECL_VARIABLE(vector_res, int, 32, 2); + DECL_VARIABLE(vector_res, int, 8, 16); + DECL_VARIABLE(vector_res, int, 16, 8); + DECL_VARIABLE(vector_res, int, 32, 4); + + clean_results (); + + /* Initialize input "vector" from "buffer". */ + VLOAD(vector, buffer, , int, s, 8, 8); + VLOAD(vector, buffer, , int, s, 16, 4); + VLOAD(vector, buffer, , int, s, 32, 2); + VLOAD(vector, buffer, q, int, s, 8, 16); + VLOAD(vector, buffer, q, int, s, 16, 8); + VLOAD(vector, buffer, q, int, s, 32, 4); + + /* Apply a saturating unary operator named INSN_NAME. */ + TEST_UNARY_SAT_OP(INSN_NAME, , int, s, 8, 8, expected_cumulative_sat, ""); + TEST_UNARY_SAT_OP(INSN_NAME, , int, s, 16, 4, expected_cumulative_sat, ""); + TEST_UNARY_SAT_OP(INSN_NAME, , int, s, 32, 2, expected_cumulative_sat, ""); + TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 8, 16, expected_cumulative_sat, ""); + TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 16, 8, expected_cumulative_sat, ""); + TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_cumulative_sat, ""); + + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx8, expected, ""); + +#ifdef EXTRA_TESTS + EXTRA_TESTS(); +#endif +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c new file mode 100644 index 0000000..f2be790 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqabs.c @@ -0,0 +1,127 @@ +#define INSN_NAME vqabs +#define TEST_MSG "VQABS/VQABSQ" + +/* Extra tests for functions requiring corner cases tests. */ +void vqabs_extra(void); +#define EXTRA_TESTS vqabs_extra + +#include "unary_sat_op.inc" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, + 0xc, 0xb, 0xa, 0x9, + 0x8, 0x7, 0x6, 0x5, + 0x4, 0x3, 0x2, 0x1 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd, + 0xc, 0xb, 0xa, 0x9 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +/* Expected values of cumulative_saturation flag. */ +int VECT_VAR(expected_cumulative_sat,int,8,8) = 0; +int VECT_VAR(expected_cumulative_sat,int,16,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,32,2) = 0; +int VECT_VAR(expected_cumulative_sat,int,8,16) = 0; +int VECT_VAR(expected_cumulative_sat,int,16,8) = 0; +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0; + +/* Expected results when input is the min negative value of the type. */ +VECT_VAR_DECL(expected_min_neg,int,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f }; +VECT_VAR_DECL(expected_min_neg,int,16,4) [] = { 0x7fff, 0x7fff, + 0x7fff, 0x7fff }; +VECT_VAR_DECL(expected_min_neg,int,32,2) [] = { 0x7fffffff, 0x7fffffff }; +VECT_VAR_DECL(expected_min_neg,int,8,16) [] = { 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f }; +VECT_VAR_DECL(expected_min_neg,int,16,8) [] = { 0x7fff, 0x7fff, + 0x7fff, 0x7fff, + 0x7fff, 0x7fff, + 0x7fff, 0x7fff }; +VECT_VAR_DECL(expected_min_neg,int,32,4) [] = { 0x7fffffff, 0x7fffffff, + 0x7fffffff, 0x7fffffff }; + +/* Expected values of cumulative_saturation flag when input is the min + negative value of the type. */ +int VECT_VAR(expected_cumulative_sat_min_neg,int,8,8) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,16,4) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,32,2) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,8,16) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,16,8) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,32,4) = 1; + +void vqabs_extra() +{ + /* No need for 64 bits variants. */ + DECL_VARIABLE(vector, int, 8, 8); + DECL_VARIABLE(vector, int, 16, 4); + DECL_VARIABLE(vector, int, 32, 2); + DECL_VARIABLE(vector, int, 8, 16); + DECL_VARIABLE(vector, int, 16, 8); + DECL_VARIABLE(vector, int, 32, 4); + + DECL_VARIABLE(vector_res, int, 8, 8); + DECL_VARIABLE(vector_res, int, 16, 4); + DECL_VARIABLE(vector_res, int, 32, 2); + DECL_VARIABLE(vector_res, int, 8, 16); + DECL_VARIABLE(vector_res, int, 16, 8); + DECL_VARIABLE(vector_res, int, 32, 4); + + clean_results (); + + /* Initialize input "vector" with min negative values to check + saturation. */ + VDUP(vector, , int, s, 8, 8, 0x80); + VDUP(vector, , int, s, 16, 4, 0x8000); + VDUP(vector, , int, s, 32, 2, 0x80000000); + VDUP(vector, q, int, s, 8, 16, 0x80); + VDUP(vector, q, int, s, 16, 8, 0x8000); + VDUP(vector, q, int, s, 32, 4, 0x80000000); + +#define MSG "min negative input" + TEST_UNARY_SAT_OP(INSN_NAME, , int, s, 8, 8, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, , int, s, 16, 4, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, , int, s, 32, 2, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 8, 16, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 16, 8, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_cumulative_sat_min_neg, MSG); + + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 16, 4, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 32, 2, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 16, 8, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 32, 4, PRIx8, expected_min_neg, MSG); +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c new file mode 100644 index 0000000..942eba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqneg.c @@ -0,0 +1,127 @@ +#define INSN_NAME vqneg +#define TEST_MSG "VQNEG/VQNEGQ" + +/* Extra tests for functions requiring corner cases tests */ +void vqneg_extra(void); +#define EXTRA_TESTS vqneg_extra + +#include "unary_sat_op.inc" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x10, 0xf, 0xe, 0xd }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x10, 0xf }; +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,int,8,16) [] = { 0x10, 0xf, 0xe, 0xd, + 0xc, 0xb, 0xa, 0x9, + 0x8, 0x7, 0x6, 0x5, + 0x4, 0x3, 0x2, 0x1 }; +VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0xf, 0xe, 0xd, + 0xc, 0xb, 0xa, 0x9 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0x10, 0xf, 0xe, 0xd }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, 0x3333333333333333 }; +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, + 0x3333333333333333 }; +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, + 0x33333333, 0x33333333 }; + +/* Expected values of cumulative_saturation flag. */ +int VECT_VAR(expected_cumulative_sat,int,8,8) = 0; +int VECT_VAR(expected_cumulative_sat,int,16,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,32,2) = 0; +int VECT_VAR(expected_cumulative_sat,int,8,16) = 0; +int VECT_VAR(expected_cumulative_sat,int,16,8) = 0; +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0; + +/* Expected results when input is the min negative value of the type. */ +VECT_VAR_DECL(expected_min_neg,int,8,8) [] = { 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f }; +VECT_VAR_DECL(expected_min_neg,int,16,4) [] = { 0x7fff, 0x7fff, + 0x7fff, 0x7fff }; +VECT_VAR_DECL(expected_min_neg,int,32,2) [] = { 0x7fffffff, 0x7fffffff }; +VECT_VAR_DECL(expected_min_neg,int,8,16) [] = { 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f }; +VECT_VAR_DECL(expected_min_neg,int,16,8) [] = { 0x7fff, 0x7fff, + 0x7fff, 0x7fff, + 0x7fff, 0x7fff, + 0x7fff, 0x7fff }; +VECT_VAR_DECL(expected_min_neg,int,32,4) [] = { 0x7fffffff, 0x7fffffff, + 0x7fffffff, 0x7fffffff }; + +/* Expected values of cumulative_saturation flag when input is the min + negative value of the type. */ +int VECT_VAR(expected_cumulative_sat_min_neg,int,8,8) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,16,4) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,32,2) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,8,16) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,16,8) = 1; +int VECT_VAR(expected_cumulative_sat_min_neg,int,32,4) = 1; + +void vqneg_extra() +{ + /* No need for 64 bits variants. */ + DECL_VARIABLE(vector, int, 8, 8); + DECL_VARIABLE(vector, int, 16, 4); + DECL_VARIABLE(vector, int, 32, 2); + DECL_VARIABLE(vector, int, 8, 16); + DECL_VARIABLE(vector, int, 16, 8); + DECL_VARIABLE(vector, int, 32, 4); + + DECL_VARIABLE(vector_res, int, 8, 8); + DECL_VARIABLE(vector_res, int, 16, 4); + DECL_VARIABLE(vector_res, int, 32, 2); + DECL_VARIABLE(vector_res, int, 8, 16); + DECL_VARIABLE(vector_res, int, 16, 8); + DECL_VARIABLE(vector_res, int, 32, 4); + + clean_results (); + + /* Initialize input "vector" with min negative values to check + saturation. */ + VDUP(vector, , int, s, 8, 8, 0x80); + VDUP(vector, , int, s, 16, 4, 0x8000); + VDUP(vector, , int, s, 32, 2, 0x80000000); + VDUP(vector, q, int, s, 8, 16, 0x80); + VDUP(vector, q, int, s, 16, 8, 0x8000); + VDUP(vector, q, int, s, 32, 4, 0x80000000); + +#define MSG "min negative input" + TEST_UNARY_SAT_OP(INSN_NAME, , int, s, 8, 8, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, , int, s, 16, 4, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, , int, s, 32, 2, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 8, 16, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 16, 8, expected_cumulative_sat_min_neg, MSG); + TEST_UNARY_SAT_OP(INSN_NAME, q, int, s, 32, 4, expected_cumulative_sat_min_neg, MSG); + + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 16, 4, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 32, 2, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 8, 16, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 16, 8, PRIx8, expected_min_neg, MSG); + CHECK(TEST_MSG, int, 32, 4, PRIx8, expected_min_neg, MSG); +}

[ARM-AArch64/testsuite,v3,06/21] Add unary saturating operators: vqabs and vqneg.

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Patch