| Message ID | 1614770488-12861-1-git-send-email-shengjiu.wang@nxp.com |
|---|---|
| State | Accepted |
| Commit | aa4890f673f9d54d3cb0ea156acfe41958ea7f08 |
| Headers | show |
| Series | ASoC: wm8962: Relax bit clock divider searching | expand |
On Fri, Mar 5, 2021 at 1:15 AM Shengjiu Wang <shengjiu.wang@nxp.com> wrote: > > With S20_3LE format case, the sysclk = rate * 384, > the bclk = rate * 20 * 2, there is no proper bclk divider > for 384 / 40, because current condition needs exact match. > So driver fails to configure the clocking: > > wm8962 3-001a: Unsupported BCLK ratio 9 > > Fix this by relaxing bitclk divider searching, so that when > no exact value can be derived from sysclk pick the closest > value greater than expected bitclk. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
On Wed, Mar 03, 2021 at 07:21:28PM +0800, Shengjiu Wang wrote: > With S20_3LE format case, the sysclk = rate * 384, > the bclk = rate * 20 * 2, there is no proper bclk divider > for 384 / 40, because current condition needs exact match. > So driver fails to configure the clocking: > > wm8962 3-001a: Unsupported BCLK ratio 9 > > Fix this by relaxing bitclk divider searching, so that when > no exact value can be derived from sysclk pick the closest > value greater than expected bitclk. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> > --- > sound/soc/codecs/wm8962.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c > index ce4666a74793..f5cd22450190 100644 > --- a/sound/soc/codecs/wm8962.c > +++ b/sound/soc/codecs/wm8962.c > @@ -2403,6 +2403,7 @@ static const int sysclk_rates[] = { > static void wm8962_configure_bclk(struct snd_soc_component *component) > { > struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); > + int best, min_diff, diff; > int dspclk, i; > int clocking2 = 0; > int clocking4 = 0; > @@ -2473,23 +2474,23 @@ static void wm8962_configure_bclk(struct snd_soc_component *component) > > dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); > Very minor nit but it would probably be nice to have some equivalent debug statement that prints out the actual BCLK we end up with. There are a couple of statements printing the requested speed, but nothing that will output what the driver actually applies after this change. Otherwise I think the change looks good. Thanks, Charles
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index ce4666a74793..f5cd22450190 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -2403,6 +2403,7 @@ static const int sysclk_rates[] = { static void wm8962_configure_bclk(struct snd_soc_component *component) { struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component); + int best, min_diff, diff; int dspclk, i; int clocking2 = 0; int clocking4 = 0; @@ -2473,23 +2474,23 @@ static void wm8962_configure_bclk(struct snd_soc_component *component) dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); - /* We're expecting an exact match */ + /* Search a proper bclk, not exact match. */ + best = 0; + min_diff = INT_MAX; for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { if (bclk_divs[i] < 0) continue; - if (dspclk / bclk_divs[i] == wm8962->bclk) { - dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n", - bclk_divs[i], wm8962->bclk); - clocking2 |= i; + diff = (dspclk / bclk_divs[i]) - wm8962->bclk; + if (diff < 0) /* Table is sorted */ break; + if (diff < min_diff) { + best = i; + min_diff = diff; } } - if (i == ARRAY_SIZE(bclk_divs)) { - dev_err(component->dev, "Unsupported BCLK ratio %d\n", - dspclk / wm8962->bclk); - return; - } + wm8962->bclk = dspclk / bclk_divs[best]; + clocking2 |= best; aif2 |= wm8962->bclk / wm8962->lrclk; dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n",
With S20_3LE format case, the sysclk = rate * 384, the bclk = rate * 20 * 2, there is no proper bclk divider for 384 / 40, because current condition needs exact match. So driver fails to configure the clocking: wm8962 3-001a: Unsupported BCLK ratio 9 Fix this by relaxing bitclk divider searching, so that when no exact value can be derived from sysclk pick the closest value greater than expected bitclk. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- sound/soc/codecs/wm8962.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-)