[RESEND,v5,3/4] arm64: dts: rockchip: Enable dmc and dfi nodes on gru.

Message ID 20210308233858.24741-3-daniel.lezcano@linaro.org
State New
Headers show
Series
  • [RESEND,v5,1/4] dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle.
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Commit Message

Daniel Lezcano March 8, 2021, 11:38 p.m.
From: Lin Huang <hl@rock-chips.com>


Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY
Interface) nodes on gru boards so we can support DDR DVFS.

Signed-off-by: Lin Huang <hl@rock-chips.com>

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>

Signed-off-by: Gaƫl PORTAY <gael.portay@collabora.com>

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

---
 .../dts/rockchip/rk3399-gru-chromebook.dtsi   |  4 ++
 arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi  | 45 +++++++++++++++++++
 .../boot/dts/rockchip/rk3399-op1-opp.dtsi     | 29 ++++++++++++
 3 files changed, 78 insertions(+)

-- 
2.17.1

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
index 1384dabbdf40..d32b015ad2cd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
@@ -398,3 +398,7 @@  ap_i2c_tp: &i2c5 {
 		rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
 	};
 };
+
+&dmc {
+	center-supply = <&ppvar_centerlogic>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 32dcaf210085..fc3dc9a4b43c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -289,6 +289,12 @@ 
 	status = "okay";
 };
 
+&dmc_opp_table {
+	opp04 {
+		opp-suspend;
+	};
+};
+
 /*
  * Set some suspend operating points to avoid OVP in suspend
  *
@@ -489,6 +495,45 @@  ap_i2c_audio: &i2c8 {
 	status = "okay";
 };
 
+&dfi {
+	status = "okay";
+};
+
+&dmc {
+	status = "okay";
+	upthreshold = <25>;
+	downdifferential = <15>;
+	rockchip,ddr3_speed_bin = <21>;
+	rockchip,pd_idle = <0x40>;
+	rockchip,sr_idle = <0x2>;
+	rockchip,sr_mc_gate_idle = <0x3>;
+	rockchip,srpd_lite_idle	= <0x4>;
+	rockchip,standby_idle = <0x2000>;
+	rockchip,dram_dll_dis_freq = <300000000>;
+	rockchip,phy_dll_dis_freq = <125000000>;
+	rockchip,auto_pd_dis_freq = <666000000>;
+	rockchip,ddr3_odt_dis_freq = <333000000>;
+	rockchip,ddr3_drv = <40>;
+	rockchip,ddr3_odt = <120>;
+	rockchip,phy_ddr3_ca_drv = <40>;
+	rockchip,phy_ddr3_dq_drv = <40>;
+	rockchip,phy_ddr3_odt = <240>;
+	rockchip,lpddr3_odt_dis_freq = <333000000>;
+	rockchip,lpddr3_drv = <34>;
+	rockchip,lpddr3_odt = <240>;
+	rockchip,phy_lpddr3_ca_drv = <40>;
+	rockchip,phy_lpddr3_dq_drv = <40>;
+	rockchip,phy_lpddr3_odt = <240>;
+	rockchip,lpddr4_odt_dis_freq = <333000000>;
+	rockchip,lpddr4_drv = <60>;
+	rockchip,lpddr4_dq_odt = <40>;
+	rockchip,lpddr4_ca_odt = <40>;
+	rockchip,phy_lpddr4_ca_drv = <40>;
+	rockchip,phy_lpddr4_ck_cs_drv = <80>;
+	rockchip,phy_lpddr4_dq_drv = <80>;
+	rockchip,phy_lpddr4_odt = <60>;
+};
+
 &sdhci {
 	/*
 	 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
index 69cc9b05baa5..c9e7032b01a8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
@@ -110,6 +110,31 @@ 
 			opp-microvolt = <1075000>;
 		};
 	};
+
+	dmc_opp_table: dmc_opp_table {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <900000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <666000000>;
+			opp-microvolt = <900000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <900000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <928000000>;
+			opp-microvolt = <900000>;
+		};
+	};
 };
 
 &cpu_l0 {
@@ -139,3 +164,7 @@ 
 &gpu {
 	operating-points-v2 = <&gpu_opp_table>;
 };
+
+&dmc {
+	operating-points-v2 = <&dmc_opp_table>;
+};