| Message ID | 20210311002854.13687-8-mirela.rabulea@oss.nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add V4L2 driver for i.MX8 JPEG Encoder/Decoder | expand |
> From: Mirela Rabulea (OSS) <mirela.rabulea@oss.nxp.com> > Sent: Thursday, March 11, 2021 8:29 AM > > Add jpeg decoder/encoder nodes, for now on imx8qxp only. > The same should work on imx8qm, but it was not tested. > > Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com> Please rebase to latest shawn/for-next branch and add the necessary clocks. I can help review when resend. Regards Aisheng > --- > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 35 > ++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > index 1d522de7b017..4f2b3edd7850 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > @@ -629,4 +629,39 @@ > }; > }; > }; > + > + img_subsys: bus@58000000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x58000000 0x0 0x58000000 0x1000000>; > + > + jpegdec: jpegdec@58400000 { > + compatible = "nxp,imx8qxp-jpgdec"; > + reg = <0x58400000 0x00050000 >; > + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, > + <&pd IMX_SC_R_MJPEG_DEC_S0>, > + <&pd IMX_SC_R_MJPEG_DEC_S1>, > + <&pd IMX_SC_R_MJPEG_DEC_S2>, > + <&pd IMX_SC_R_MJPEG_DEC_S3>; > + }; > + > + jpegenc: jpegenc@58450000 { > + compatible = "nxp,imx8qxp-jpgenc"; > + reg = <0x58450000 0x00050000 >; > + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, > + <&pd IMX_SC_R_MJPEG_ENC_S0>, > + <&pd IMX_SC_R_MJPEG_ENC_S1>, > + <&pd IMX_SC_R_MJPEG_ENC_S2>, > + <&pd IMX_SC_R_MJPEG_ENC_S3>; > + }; > + }; > }; > -- > 2.17.1
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 1d522de7b017..4f2b3edd7850 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -629,4 +629,39 @@ }; }; }; + + img_subsys: bus@58000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x58000000 0x0 0x58000000 0x1000000>; + + jpegdec: jpegdec@58400000 { + compatible = "nxp,imx8qxp-jpgdec"; + reg = <0x58400000 0x00050000 >; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, + <&pd IMX_SC_R_MJPEG_DEC_S0>, + <&pd IMX_SC_R_MJPEG_DEC_S1>, + <&pd IMX_SC_R_MJPEG_DEC_S2>, + <&pd IMX_SC_R_MJPEG_DEC_S3>; + }; + + jpegenc: jpegenc@58450000 { + compatible = "nxp,imx8qxp-jpgenc"; + reg = <0x58450000 0x00050000 >; + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, + <&pd IMX_SC_R_MJPEG_ENC_S0>, + <&pd IMX_SC_R_MJPEG_ENC_S1>, + <&pd IMX_SC_R_MJPEG_ENC_S2>, + <&pd IMX_SC_R_MJPEG_ENC_S3>; + }; + }; };