diff mbox series

[V2] cpufreq: Rudimentary typos fix in the file s5pv210-cpufreq.c

Message ID 20210312232621.2083-1-unixbhaskar@gmail.com
State Superseded
Headers show
Series [V2] cpufreq: Rudimentary typos fix in the file s5pv210-cpufreq.c | expand

Commit Message

Bhaskar Chowdhury March 12, 2021, 11:26 p.m. UTC
s/untile/until/
s/souce/source/
s/divier/divider/

Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
 Changes from V1:
   Krzysztof spotted a grammatical flaw left over ...so corrected..

 drivers/cpufreq/s5pv210-cpufreq.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

--
2.26.2

Comments

Tom Saeger March 13, 2021, 12:16 a.m. UTC | #1
On Sat, Mar 13, 2021 at 04:56:21AM +0530, Bhaskar Chowdhury wrote:

sent a few additional typo fixes to your V1, can you add those to your patch?

Regards,

--Tom
Bhaskar Chowdhury March 13, 2021, 12:50 a.m. UTC | #2
On 17:16 Fri 12 Mar 2021, Tom Saeger wrote:
>On Sat, Mar 13, 2021 at 04:56:21AM +0530, Bhaskar Chowdhury wrote:

>

>sent a few additional typo fixes to your V1, can you add those to your patch?

>

>Regards,

>

>--Tom


Thanks, I have already sent out a V2 in public...I might make a V3 with your
changes too...did you sent it to ???
Randy Dunlap March 13, 2021, 12:57 a.m. UTC | #3
On 3/12/21 4:50 PM, Bhaskar Chowdhury wrote:
> On 17:16 Fri 12 Mar 2021, Tom Saeger wrote:
>> On Sat, Mar 13, 2021 at 04:56:21AM +0530, Bhaskar Chowdhury wrote:
>>
>> sent a few additional typo fixes to your V1, can you add those to your patch?
>>
>> Regards,
>>
>> --Tom
> 
> Thanks, I have already sent out a V2 in public...I might make a V3 with your
> changes too...did you sent it to ???

It was just a reply to your v1 patch.
Tom Saeger March 13, 2021, 2:59 a.m. UTC | #4
On Fri, Mar 12, 2021 at 04:57:07PM -0800, Randy Dunlap wrote:
> On 3/12/21 4:50 PM, Bhaskar Chowdhury wrote:
> > On 17:16 Fri 12 Mar 2021, Tom Saeger wrote:
> >> On Sat, Mar 13, 2021 at 04:56:21AM +0530, Bhaskar Chowdhury wrote:
> >>
> >> sent a few additional typo fixes to your V1, can you add those to your patch?
> >>
> >> Regards,
> >>
> >> --Tom
> > 
> > Thanks, I have already sent out a V2 in public...I might make a V3 with your
> > changes too...did you sent it to ???
> 
> It was just a reply to your v1 patch.
> 
> -- 
> ~Randy
> 

Bhaskar,

Here you go...

V2 additions:

diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
index af1ac3f6e4b8..73110b005716 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -91,7 +91,7 @@ static DEFINE_MUTEX(set_freq_lock);
 /* Use 800MHz when entering sleep mode */
 #define SLEEP_FREQ     (800 * 1000)

-/* Tracks if cpu freqency can be updated anymore */
+/* Tracks if cpu frequency can be updated anymore */
 static bool no_cpufreq_access;

 /*
@@ -190,7 +190,7 @@ static u32 clkdiv_val[5][11] = {

 /*
  * This function set DRAM refresh counter
- * accoriding to operating frequency of DRAM
+ * according to operating frequency of DRAM
  * ch: DMC port number 0 or 1
  * freq: Operating frequency of DRAM(KHz)
  */
@@ -320,7 +320,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)

                /*
                 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
-                * true refresh counter is already programed in upper
+                * true refresh counter is already programmed in upper
                 * code. 0x287@83Mhz
                 */
                if (!bus_speed_changing)
diff mbox series

Patch

diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
index 69786e5bbf05..af1ac3f6e4b8 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -378,7 +378,7 @@  static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
 		/*
 		 * 6. Turn on APLL
 		 * 6-1. Set PMS values
-		 * 6-2. Wait untile the PLL is locked
+		 * 6-2. Wait until the PLL is locked
 		 */
 		if (index == L0)
 			writel_relaxed(APLL_VAL_1000, S5P_APLL_CON);
@@ -390,7 +390,7 @@  static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
 		} while (!(reg & (0x1 << 29)));

 		/*
-		 * 7. Change souce clock from SCLKMPLL(667Mhz)
+		 * 7. Change source clock from SCLKMPLL(667Mhz)
 		 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
 		 * (667/4=166)->(200/4=50)Mhz
 		 */
@@ -439,7 +439,7 @@  static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
 	}

 	/*
-	 * L4 level need to change memory bus speed, hence onedram clock divier
+	 * L4 level needs to change memory bus speed, hence onedram clock divider
 	 * and memory refresh parameter should be changed
 	 */
 	if (bus_speed_changing) {