| Message ID | 1415377536-12841-8-git-send-email-mark.rutland@arm.com |
|---|---|
| State | New |
| Headers | show |
Hi Mark, On Fri, Nov 07, 2014 at 04:25:32PM +0000, Mark Rutland wrote: > To describe the various ways CPU PMU interrupts might be wired up, we > can refer to the topology information in the device tree. > > This patch adds a new property to the PMU binding, interrupts-affinity, > which describes the relationship between CPUs and interrupts. This > information is necessary to handle systems with heterogeneous PMU > implementations (e.g. big.LITTLE). Documentation is added describing the > use of said property. I'm not entirely comfortable with using interrupt affinity to convey PMU affinity. It seems perfectly plausible for somebody to play the usual trick of ORing all the irq lines together, despite having a big/little PMU configuration. Can you describe such a system with this binding? > +Example 2 (Multiple clusters with single interrupts): > + > +cpus { > + #address-cells = <1>; > + #size-cells = <1>; > + > + CPU0: cpu@0 { > + reg = <0x0>; > + compatible = "arm,cortex-a15-pmu"; > + }; > + > + CPU1: cpu@1 { > + reg = <0x1>; > + compatible = "arm,cotex-a15-pmu"; cortex > + }; > + > + CPU100: cpu@100 { > + reg = <0x100>; > + compatible = "arm,cortex-a7-pmu"; > + }; > + > + cpu-map { > + cluster0 { > + CORE_0_0: core0 { > + cpu = <&CPU0>; > + }; > + CORE_0_1: core1 { > + cpu = <&CPU1>; > + }; > + }; > + cluster1 { > + CORE_1_0: core0 { > + cpu = <&CPU100>; > + }; > + }; > + }; > +}; > + > +pmu_a15 { > + compatible = "arm,cortex-a15-pmu"; > + interrupts = <100>, <101>; > + interrupts-affinity = <&CORE0>, <&CORE1>; > +}; > + > +pmu_a7 { > + compatible = "arm,cortex-a7-pmu"; > + interrupts = <105>; > + interrupts-affinity = <&CORE_1_0>; > +}; > + > +Example 3 (Multiple clusters with per-cpu interrupts): > + > +cpus { > + #address-cells = <1>; > + #size-cells = <1>; > + > + CPU0: cpu@0 { > + reg = <0x0>; > + compatible = "arm,cortex-a15-pmu"; > + }; > + > + CPU1: cpu@1 { > + reg = <0x1>; > + compatible = "arm,cotex-a15-pmu"; Same here. Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
On Fri, Nov 7, 2014 at 10:25 AM, Mark Rutland <mark.rutland@arm.com> wrote: > To describe the various ways CPU PMU interrupts might be wired up, we > can refer to the topology information in the device tree. > > This patch adds a new property to the PMU binding, interrupts-affinity, > which describes the relationship between CPUs and interrupts. This > information is necessary to handle systems with heterogeneous PMU > implementations (e.g. big.LITTLE). Documentation is added describing the > use of said property. > > Signed-off-by: Mark Rutland <mark.rutland@arm.com> > --- > Documentation/devicetree/bindings/arm/pmu.txt | 104 +++++++++++++++++++++++++- > 1 file changed, 103 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt > index 75ef91d..23a0675 100644 > --- a/Documentation/devicetree/bindings/arm/pmu.txt > +++ b/Documentation/devicetree/bindings/arm/pmu.txt > @@ -24,12 +24,114 @@ Required properties: > > Optional properties: > > +- interrupts-affinity : A list of phandles to topology nodes (see topology.txt) describing > + the set of CPUs associated with the interrupt at the same index. Are there cases beyond PMUs we need to handle? I would think so, so we should document this generically. > - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd > events. > > -Example: > +Example 1 (A single CPU): Isn't this a single cluster of 2 cpus? > > pmu { > compatible = "arm,cortex-a9-pmu"; > interrupts = <100 101>; > }; > + > +Example 2 (Multiple clusters with single interrupts): The meaning of single could be made a bit more clear especially if you consider Will's case. But I haven't really thought of better wording... > + > +cpus { > + #address-cells = <1>; > + #size-cells = <1>; > + > + CPU0: cpu@0 { > + reg = <0x0>; > + compatible = "arm,cortex-a15-pmu"; > + }; > + > + CPU1: cpu@1 { > + reg = <0x1>; > + compatible = "arm,cotex-a15-pmu"; > + }; > + > + CPU100: cpu@100 { > + reg = <0x100>; > + compatible = "arm,cortex-a7-pmu"; > + }; > + > + cpu-map { > + cluster0 { > + CORE_0_0: core0 { > + cpu = <&CPU0>; > + }; > + CORE_0_1: core1 { > + cpu = <&CPU1>; > + }; > + }; > + cluster1 { > + CORE_1_0: core0 { > + cpu = <&CPU100>; > + }; > + }; > + }; > +}; > + > +pmu_a15 { > + compatible = "arm,cortex-a15-pmu"; > + interrupts = <100>, <101>; > + interrupts-affinity = <&CORE0>, <&CORE1>; The phandle names are wrong here. > +}; > + > +pmu_a7 { > + compatible = "arm,cortex-a7-pmu"; > + interrupts = <105>; > + interrupts-affinity = <&CORE_1_0>; > +}; > + > +Example 3 (Multiple clusters with per-cpu interrupts): > + > +cpus { > + #address-cells = <1>; > + #size-cells = <1>; > + > + CPU0: cpu@0 { > + reg = <0x0>; > + compatible = "arm,cortex-a15-pmu"; > + }; > + > + CPU1: cpu@1 { > + reg = <0x1>; > + compatible = "arm,cotex-a15-pmu"; > + }; > + > + CPU100: cpu@100 { > + reg = <0x100>; > + compatible = "arm,cortex-a7-pmu"; > + }; > + > + cpu-map { > + CLUSTER0: cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + core1 { > + cpu = <&CPU1>; > + }; > + }; > + CLUSTER1: cluster1 { > + core0 { > + cpu = <&CPU100>; > + }; > + }; > + }; > +}; > + > +pmu_a15 { > + compatible = "arm,cortex-a15-pmu"; > + interrupts = <100>; > + interrupts-affinity = <&CLUSTER0>; > +}; > + > +pmu_a7 { > + compatible = "arm,cortex-a7-pmu"; > + interrupts = <105>; > + interrupts-affinity = <&CLUSTER1>; > +}; > -- > 1.9.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Hi Rob, I appear to have typo'd your address when posting this. Sorry about that; I'll make sure it doesn't happen again. On Mon, Nov 17, 2014 at 02:32:57PM +0000, Rob Herring wrote: > On Fri, Nov 7, 2014 at 10:25 AM, Mark Rutland <mark.rutland@arm.com> wrote: > > To describe the various ways CPU PMU interrupts might be wired up, we > > can refer to the topology information in the device tree. > > > > This patch adds a new property to the PMU binding, interrupts-affinity, > > which describes the relationship between CPUs and interrupts. This > > information is necessary to handle systems with heterogeneous PMU > > implementations (e.g. big.LITTLE). Documentation is added describing the > > use of said property. > > > > Signed-off-by: Mark Rutland <mark.rutland@arm.com> > > --- > > Documentation/devicetree/bindings/arm/pmu.txt | 104 +++++++++++++++++++++++++- > > 1 file changed, 103 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt > > index 75ef91d..23a0675 100644 > > --- a/Documentation/devicetree/bindings/arm/pmu.txt > > +++ b/Documentation/devicetree/bindings/arm/pmu.txt > > @@ -24,12 +24,114 @@ Required properties: > > > > Optional properties: > > > > +- interrupts-affinity : A list of phandles to topology nodes (see topology.txt) describing > > + the set of CPUs associated with the interrupt at the same index. > > Are there cases beyond PMUs we need to handle? I would think so, so we > should document this generically. That was what I tried way back when I first tried to upstream all of this, but in the mean time I've not encountered other devices which are really CPU-affine which use SPIs and hence need a CPU<->IRQ relationship described. That said, I'm happy to document whatever approach for referring to a set of CPUs that we settle on, if that seems more general than PMU IRQ mapping. > > -Example: > > +Example 1 (A single CPU): > > Isn't this a single cluster of 2 cpus? Yes, it is. My bad. > > pmu { > > compatible = "arm,cortex-a9-pmu"; > > interrupts = <100 101>; > > }; > > + > > +Example 2 (Multiple clusters with single interrupts): > > The meaning of single could be made a bit more clear especially if you > consider Will's case. But I haven't really thought of better > wording... How about "A cluster of homogeneous CPUs"? > > + > > +cpus { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + CPU0: cpu@0 { > > + reg = <0x0>; > > + compatible = "arm,cortex-a15-pmu"; > > + }; > > + > > + CPU1: cpu@1 { > > + reg = <0x1>; > > + compatible = "arm,cotex-a15-pmu"; > > + }; > > + > > + CPU100: cpu@100 { > > + reg = <0x100>; > > + compatible = "arm,cortex-a7-pmu"; > > + }; > > + > > + cpu-map { > > + cluster0 { > > + CORE_0_0: core0 { > > + cpu = <&CPU0>; > > + }; > > + CORE_0_1: core1 { > > + cpu = <&CPU1>; > > + }; > > + }; > > + cluster1 { > > + CORE_1_0: core0 { > > + cpu = <&CPU100>; > > + }; > > + }; > > + }; > > +}; > > + > > +pmu_a15 { > > + compatible = "arm,cortex-a15-pmu"; > > + interrupts = <100>, <101>; > > + interrupts-affinity = <&CORE0>, <&CORE1>; > > The phandle names are wrong here. Whoops. I've fixed that up locally now. Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt index 75ef91d..23a0675 100644 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ b/Documentation/devicetree/bindings/arm/pmu.txt @@ -24,12 +24,114 @@ Required properties: Optional properties: +- interrupts-affinity : A list of phandles to topology nodes (see topology.txt) describing + the set of CPUs associated with the interrupt at the same index. - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd events. -Example: +Example 1 (A single CPU): pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <100 101>; }; + +Example 2 (Multiple clusters with single interrupts): + +cpus { + #address-cells = <1>; + #size-cells = <1>; + + CPU0: cpu@0 { + reg = <0x0>; + compatible = "arm,cortex-a15-pmu"; + }; + + CPU1: cpu@1 { + reg = <0x1>; + compatible = "arm,cotex-a15-pmu"; + }; + + CPU100: cpu@100 { + reg = <0x100>; + compatible = "arm,cortex-a7-pmu"; + }; + + cpu-map { + cluster0 { + CORE_0_0: core0 { + cpu = <&CPU0>; + }; + CORE_0_1: core1 { + cpu = <&CPU1>; + }; + }; + cluster1 { + CORE_1_0: core0 { + cpu = <&CPU100>; + }; + }; + }; +}; + +pmu_a15 { + compatible = "arm,cortex-a15-pmu"; + interrupts = <100>, <101>; + interrupts-affinity = <&CORE0>, <&CORE1>; +}; + +pmu_a7 { + compatible = "arm,cortex-a7-pmu"; + interrupts = <105>; + interrupts-affinity = <&CORE_1_0>; +}; + +Example 3 (Multiple clusters with per-cpu interrupts): + +cpus { + #address-cells = <1>; + #size-cells = <1>; + + CPU0: cpu@0 { + reg = <0x0>; + compatible = "arm,cortex-a15-pmu"; + }; + + CPU1: cpu@1 { + reg = <0x1>; + compatible = "arm,cotex-a15-pmu"; + }; + + CPU100: cpu@100 { + reg = <0x100>; + compatible = "arm,cortex-a7-pmu"; + }; + + cpu-map { + CLUSTER0: cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + CLUSTER1: cluster1 { + core0 { + cpu = <&CPU100>; + }; + }; + }; +}; + +pmu_a15 { + compatible = "arm,cortex-a15-pmu"; + interrupts = <100>; + interrupts-affinity = <&CLUSTER0>; +}; + +pmu_a7 { + compatible = "arm,cortex-a7-pmu"; + interrupts = <105>; + interrupts-affinity = <&CLUSTER1>; +};
To describe the various ways CPU PMU interrupts might be wired up, we can refer to the topology information in the device tree. This patch adds a new property to the PMU binding, interrupts-affinity, which describes the relationship between CPUs and interrupts. This information is necessary to handle systems with heterogeneous PMU implementations (e.g. big.LITTLE). Documentation is added describing the use of said property. Signed-off-by: Mark Rutland <mark.rutland@arm.com> --- Documentation/devicetree/bindings/arm/pmu.txt | 104 +++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-)