@@ -242,6 +242,20 @@
#clock-cells = <1>;
};
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt6779-mmc";
+ reg = <0 0x11230000 0 0x10000>,
+ <0 0x11f50000 0 0x10000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0>,
+ <&infracfg_ao CLK_INFRA_MSDC0>,
+ <&infracfg_ao CLK_INFRA_MSDC0_SCK>,
+ <&infracfg_ao CLK_INFRA_AES_UFSFDE>;
+ clock-names = "source", "hclk", "source_cg",
+ "crypto";
+ status = "disabled";
+ };
+
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt6779-mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;