From patchwork Tue Apr 20 08:27:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 424562 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp206990jao; Tue, 20 Apr 2021 02:29:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyNBgQhFcd+17KJ0NW+eCtigMAx8cDkHc9YTeTTpKRH9XjZo2qgo97JlQ9khhjlqrhzZqTb X-Received: by 2002:a17:907:7051:: with SMTP id ws17mr26694460ejb.498.1618910950709; Tue, 20 Apr 2021 02:29:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618910950; cv=none; d=google.com; s=arc-20160816; b=ZHxL7jmpjiUem3wRPTExn9LI7B91KY9jN4WJ7gi125+WsyAf3qf3zPnWGB05EYBg9f I1YoVvMwZkzLYqcx3ELP12YI9RshR2wsuUCqRQl7G+jGHt1pVBkmBfqdLgsKRrbGYgTv hTVyZlmkd288wiK1faVqKN4Na9lkqMUyMno6AfD+QAkS2G/zULqBHRlrAp0NHkbIhxsh kmKJBj4BOt810rQlVtAlfPnCl45PPWL8iFSQXhDXUEHk1WCV6QRtuwehinVxh2fA5itq YK16B5iGmOXkMFZa/WuJAxEBYmkjThACaunclA/N7p1ABpsICQG8aIile4Im3Tnte9rH Oydg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lZkgU0fxhYv2WpMn0yIyept9dGbJaF8kLuRZsxtlvng=; b=TUCA+IjFdRpGHvGRf+LAnT0lsGHzB2+8xb9hkqrg2V5F8Ea1MWqgciYN6AKAy861Vp M9JauamZfC3khuiGV8oo3TUgMKbdoN6lDJoQJi6XN66a1mo4rPN1Ro5YheyE/r0yhohu coAaV2MtSQENYH7rUW57onE/Z1Zi9E/rwfcdb8cbxXcEflN3wRxTQ3BmfokUnmAWkCu5 p+/aXZBgC87rdku3udIS7CQe4S37jEDbbQ34+SSeIgwYUiZJDsd7K84Wn5JA7ZXN4AI7 +B7wJshi/Jc5Gxd2M3V8V99YTbEumFKQqXbD/h9LsWeEDjoNCs/hmUECWZEtvoKT/wLO QW2A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ds2si13913381ejc.749.2021.04.20.02.29.10; Tue, 20 Apr 2021 02:29:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbhDTJ3k (ORCPT + 4 others); Tue, 20 Apr 2021 05:29:40 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:16486 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229494AbhDTJ3j (ORCPT ); Tue, 20 Apr 2021 05:29:39 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FPdc54Q90zrffL; Tue, 20 Apr 2021 17:26:45 +0800 (CST) Received: from A2006125610.china.huawei.com (10.47.83.26) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Tue, 20 Apr 2021 17:28:57 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , Subject: [PATCH v3 09/10] iommu/arm-smmu: Get associated RMR info and install bypass SMR Date: Tue, 20 Apr 2021 10:27:50 +0200 Message-ID: <20210420082751.1829-10-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210420082751.1829-1-shameerali.kolothum.thodi@huawei.com> References: <20210420082751.1829-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.26] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org From: Jon Nettleton Check if there is any RMR info associated with the devices behind the SMMU and if any, install bypass SMRs for them. This is to keep any ongoing traffic associated with these devices alive when we enable/reset SMMU during probe(). Signed-off-by: Jon Nettleton Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 42 +++++++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 ++ 2 files changed, 44 insertions(+) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index d8c6bfde6a61..4d2f91626d87 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -2102,6 +2102,43 @@ err_reset_platform_ops: __maybe_unused; return err; } +static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu) +{ + struct iommu_rmr *e; + int i, cnt = 0; + u32 smr; + + for (i = 0; i < smmu->num_mapping_groups; i++) { + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); + if (!FIELD_GET(ARM_SMMU_SMR_VALID, smr)) + continue; + + list_for_each_entry(e, &smmu->rmr_list, list) { + if (FIELD_GET(ARM_SMMU_SMR_ID, smr) != e->sid) + continue; + + smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); + smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); + smmu->smrs[i].valid = true; + + smmu->s2crs[i].type = S2CR_TYPE_BYPASS; + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; + smmu->s2crs[i].cbndx = 0xff; + + cnt++; + } + } + + dev_notice(smmu->dev, "\tpreserved %d boot mapping%s\n", cnt, + cnt == 1 ? "" : "s"); +} + +static int arm_smmu_get_rmr(struct arm_smmu_device *smmu) +{ + INIT_LIST_HEAD(&smmu->rmr_list); + return iommu_dma_get_rmrs(dev_fwnode(smmu->dev), &smmu->rmr_list); +} + static int arm_smmu_device_probe(struct platform_device *pdev) { struct resource *res; @@ -2231,6 +2268,11 @@ static int arm_smmu_device_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, smmu); + + /* Check for RMRs and install bypass SMRs if any */ + if (!arm_smmu_get_rmr(smmu)) + arm_smmu_rmr_install_bypass_smr(smmu); + arm_smmu_device_reset(smmu); arm_smmu_test_smr_masks(smmu); diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index d2a2d1bc58ba..ca9559eb8733 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -326,6 +326,8 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + + struct list_head rmr_list; }; enum arm_smmu_context_fmt {