| Message ID | 20210420081153.17020-5-nava.manne@xilinx.com |
|---|---|
| State | New |
| Headers | show |
| Series | misc: Add afi config drivers support. | expand |
Hi Rob, Please find my response inline. > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Tuesday, April 20, 2021 7:29 PM > To: Nava kishore Manne <navam@xilinx.com> > Cc: robh+dt@kernel.org; Tejas Patel <tejasp@xlnx.xilinx.com>; Michal Simek > <michals@xilinx.com>; Rajan Vaja <RAJANV@xilinx.com>; linux-arm- > kernel@lists.infradead.org; Amit Sunil Dhamne <amitsuni@xilinx.com>; > Dragan Cvetic <draganc@xilinx.com>; Derek Kiernan <dkiernan@xilinx.com>; > Jolly Shah <JOLLYS@xilinx.com>; git <git@xilinx.com>; > chinnikishore369@gmail.com; arnd@arndb.de; > gregkh@linuxfoundation.org; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org > Subject: Re: [PATCH 4/5] misc: doc: Add binding doc for the zynqmp afi config > driver > > On Tue, 20 Apr 2021 13:41:52 +0530, Nava kishore Manne wrote: > > This patch adds the binding document for the zynqmp afi config driver. > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> > > --- > > .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++ > > 1 file changed, 136 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m > dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > Thanks for the providing the update on the new features > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi- > fpga.example.dt.yaml:0:0: /example-0/firmware/zynqmp-firmware: failed to > match any schema with compatible: ['xlnx,zynqmp-firmware'] > Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi- > fpga.example.dt.yaml:0:0: /example-0/firmware/zynqmp-firmware/afi: > failed to match any schema with compatible: ['xlnx,afi-fpga'] > > See https://patchwork.ozlabs.org/patch/1468230 > > This check can fail if there are any dependencies. The base for a patch series > is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above error(s), > then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. Will fix in v2. Regards, Navakishore.
Hi Rob, Thanks for the review. Please find my response inline. > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Tuesday, April 20, 2021 7:45 PM > To: Nava kishore Manne <navam@xilinx.com> > Cc: Michal Simek <michals@xilinx.com>; Derek Kiernan > <dkiernan@xilinx.com>; Dragan Cvetic <draganc@xilinx.com>; > arnd@arndb.de; gregkh@linuxfoundation.org; Rajan Vaja > <RAJANV@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; Tejas Patel > <tejasp@xlnx.xilinx.com>; Amit Sunil Dhamne <amitsuni@xilinx.com>; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; chinnikishore369@gmail.com; git <git@xilinx.com> > Subject: Re: [PATCH 4/5] misc: doc: Add binding doc for the zynqmp afi config > driver > > On Tue, Apr 20, 2021 at 01:41:52PM +0530, Nava kishore Manne wrote: > > This patch adds the binding document for the zynqmp afi config driver. > > Bindings are for h/w blocks, not drivers. > This Binding are for h/w blocks (PS-PL bus width configurations) For more info please refer the below links. https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf (Page No: 54) https://www.xilinx.com/support/documentation/ip_documentation/zynq_ultra_ps_e/v3_2/pg201-zynq-ultrascale-plus-processing-system.pdf (Page No: 42). Please let me know if you need more info.. > > > > Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> > > --- > > .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++ > > 1 file changed, 136 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml > > b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml > > new file mode 100644 > > index 000000000000..3ae22096b22a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi- > fpga.yaml > > @@ -0,0 +1,136 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/misc/xlnx,zynqmp-afi-fpga.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Xilinx ZynqMP AFI interface Manager. > > + > > +maintainers: > > + - Nava kishore Manne <nava.manne@xilinx.com> > > + > > +description: | > > + The Zynq UltraScale+ MPSoC Processing System core provides access > > +from PL > > + masters to PS internal peripherals, and memory through AXI FIFO > > +interface(AFI) > > + interfaces. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - xlnx,zynqmp-afi-fpga > > + > > + config-afi: > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + description: | > > + Pairs of <regid value > > > + The possible values of regid and values are > > + regid - Regids of the register to be written possible values > > If we wanted sequences of register accesses in DT, we'd have a generic > mechanism to do so. > I will try to find a better way, will get back you on this Regards, Navakishore.
diff --git a/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml new file mode 100644 index 000000000000..3ae22096b22a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,zynqmp-afi-fpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx ZynqMP AFI interface Manager. + +maintainers: + - Nava kishore Manne <nava.manne@xilinx.com> + +description: | + The Zynq UltraScale+ MPSoC Processing System core provides access from PL + masters to PS internal peripherals, and memory through AXI FIFO interface(AFI) + interfaces. + +properties: + compatible: + items: + - enum: + - xlnx,zynqmp-afi-fpga + + config-afi: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Pairs of <regid value > + The possible values of regid and values are + regid - Regids of the register to be written possible values + 0- AFIFM0_RDCTRL + 1- AFIFM0_WRCTRL + 2- AFIFM1_RDCTRL + 3- AFIFM1_WRCTRL + 4- AFIFM2_RDCTRL + 5- AFIFM2_WRCTRL + 6- AFIFM3_RDCTRL + 7- AFIFM3_WRCTRL + 8- AFIFM4_RDCTRL + 9- AFIFM4_WRCTRL + 10- AFIFM5_RDCTRL + 11- AFIFM5_WRCTRL + 12- AFIFM6_RDCTRL + 13- AFIFM6_WRCTRL + 14- AFIFS + 15- AFIFS_SS2 + value - Array of values to be written. + for FM0_RDCTRL(0) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM0_WRCTRL(1) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM1_RDCTRL(2) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM1_WRCTRL(3) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM2_RDCTRL(4) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM2_WRCTRL(5) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM3_RDCTRL(6) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM3_WRCTRL(7) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM4_RDCTRL(8) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM4_WRCTRL(9) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM5_RDCTRL(10) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM5_WRCTRL(11) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM6_RDCTRL(12) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM6_WRCTRL(13) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for AFI_FA(14) + dw_ss1_sel bits (11:10) + dw_ss0_sel bits (9:8) + 0x0 - 32-bit AXI data width + 0x1 - 64-bit AXI data width + 0x2 - 128-bit AXI data width + All other bits are 0 write ignored. + + for AFI_FA(15) selects for ss2AXI data width valid values + 0x000 - 32-bit AXI data width + 0x100 - 64-bit AXI data width + 0x200 - 128-bit AXI data width + minItems: 1 + maxItems: 15 + +required: + - compatible + - config-afi + +additionalProperties: false + +examples: + - | + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + afi0: afi { + compatible = "xlnx,afi-fpga"; + config-afi = <0 2>, <1 1>, <2 1>; + }; + }; + }; + +...
This patch adds the binding document for the zynqmp afi config driver. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> --- .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml