@@ -331,7 +331,7 @@ static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
- u32 ccr, cr, addr_max;
+ u32 ccr, cr;
int timeout, err = 0;
dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
@@ -343,18 +343,6 @@ static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
if (err)
goto abort;
- addr_max = op->addr.val + op->data.nbytes + 1;
-
- if (op->data.dir == SPI_MEM_DATA_IN) {
- if (addr_max < qspi->mm_size &&
- op->addr.buswidth)
- qspi->fmode = CCR_FMODE_MM;
- else
- qspi->fmode = CCR_FMODE_INDR;
- } else {
- qspi->fmode = CCR_FMODE_INDW;
- }
-
cr = readl_relaxed(qspi->io_base + QSPI_CR);
cr &= ~CR_PRESC_MASK & ~CR_FSEL;
cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
@@ -364,8 +352,6 @@ static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
if (op->data.nbytes)
writel_relaxed(op->data.nbytes - 1,
qspi->io_base + QSPI_DLR);
- else
- qspi->fmode = CCR_FMODE_INDW;
ccr = qspi->fmode;
ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
@@ -441,6 +427,11 @@ static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
}
mutex_lock(&qspi->lock);
+ if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
+ qspi->fmode = CCR_FMODE_INDR;
+ else
+ qspi->fmode = CCR_FMODE_INDW;
+
ret = stm32_qspi_send(mem, op);
mutex_unlock(&qspi->lock);
@@ -450,6 +441,64 @@ static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
return ret;
}
+static int stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+ struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
+
+ if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
+ return -EOPNOTSUPP;
+
+ /* should never happen, as mm_base == null is an error probe exit condition */
+ if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
+ return -EOPNOTSUPP;
+
+ if (!qspi->mm_size)
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
+static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ u64 offs, size_t len, void *buf)
+{
+ struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
+ struct spi_mem_op op;
+ u32 addr_max;
+ int ret;
+
+ ret = pm_runtime_get_sync(qspi->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(qspi->dev);
+ return ret;
+ }
+
+ mutex_lock(&qspi->lock);
+ /* make a local copy of desc op_tmpl and complete dirmap rdesc
+ * spi_mem_op template with offs, len and *buf in order to get
+ * all needed transfer information into struct spi_mem_op
+ */
+ memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
+ dev_dbg(qspi->dev, "%s len = 0x%x offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
+
+ op.data.nbytes = len;
+ op.addr.val = desc->info.offset + offs;
+ op.data.buf.in = buf;
+
+ addr_max = op.addr.val + op.data.nbytes + 1;
+ if (addr_max < qspi->mm_size && op.addr.buswidth)
+ qspi->fmode = CCR_FMODE_MM;
+ else
+ qspi->fmode = CCR_FMODE_INDR;
+
+ ret = stm32_qspi_send(desc->mem, &op);
+ mutex_unlock(&qspi->lock);
+
+ pm_runtime_mark_last_busy(qspi->dev);
+ pm_runtime_put_autosuspend(qspi->dev);
+
+ return ret ?: len;
+}
+
static int stm32_qspi_setup(struct spi_device *spi)
{
struct spi_controller *ctrl = spi->master;
@@ -555,7 +604,9 @@ static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
* to check supported mode.
*/
static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
- .exec_op = stm32_qspi_exec_op,
+ .exec_op = stm32_qspi_exec_op,
+ .dirmap_create = stm32_qspi_dirmap_create,
+ .dirmap_read = stm32_qspi_dirmap_read,
};
static int stm32_qspi_probe(struct platform_device *pdev)