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[9/9] coresight: Documenting reference to generic PD bindings

Message ID 1420562233-2015-10-git-send-email-mathieu.poirier@linaro.org
State New
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Commit Message

Mathieu Poirier Jan. 6, 2015, 4:37 p.m. UTC 
From: Mathieu Poirier <mathieu.poirier@linaro.org>

Each coresight block can be part of a power domain.  Using the
generic power domain subsystems to manage power to individual
domains guarantes that coresight operations won't be interrupted
by other components.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 Documentation/devicetree/bindings/arm/coresight.txt | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index d790f49066f3..27f96f0d36ef 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -50,6 +50,10 @@  its hardware characteristcs.
 	* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
 	  source is considered to belong to CPU0.
 
+	* power-domains: a handle to the generic power domain node this
+	  coresight block is affined to.  When omitted the component is
+	  assumed to always be powered.
+
 * Optional property for TMC:
 
 	* arm,buffer-size: size of contiguous buffer space for TMC ETR