diff mbox series

[8/9] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1]

Message ID 20210509151618.2331764-9-f4bug@amsat.org
State New
Headers show
Series [1/9] accel/tcg: Replace g_new() + memcpy() by g_memdup() | expand

Commit Message

Philippe Mathieu-Daudé May 9, 2021, 3:16 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>


Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

---
 accel/tcg/cputlb.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

-- 
2.26.3

Comments

Richard Henderson May 25, 2021, 1:50 p.m. UTC | #1 
On 5/9/21 8:16 AM, Philippe Mathieu-Daudé wrote:
> From: Richard Henderson<richard.henderson@linaro.org>

> 

> Signed-off-by: Richard Henderson<richard.henderson@linaro.org>

> Message-Id:<20210508201640.1045808-1-richard.henderson@linaro.org>

> [PMD: Split from bigger patch]

> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>

> ---

>   accel/tcg/cputlb.c | 12 ++++++------

>   1 file changed, 6 insertions(+), 6 deletions(-)


Rename to match tlb_flush_range_locked.


r~
diff mbox series

Patch

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 47c83f0fc83..ad0e44bce63 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -816,8 +816,8 @@  static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu,
     tlb_flush_range_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon));
 }
 
-static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu,
-                                                  run_on_cpu_data data)
+static void tlb_flush_range_by_mmuidx_async_1(CPUState *cpu,
+                                              run_on_cpu_data data)
 {
     TLBFlushRangeData *d = data.host_ptr;
     tlb_flush_range_by_mmuidx_async_0(cpu, *d);
@@ -858,7 +858,7 @@  void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr,
     } else {
         /* Otherwise allocate a structure, freed by the worker.  */
         TLBFlushRangeData *p = g_memdup(&d, sizeof(d));
-        async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2,
+        async_run_on_cpu(cpu, tlb_flush_range_by_mmuidx_async_1,
                          RUN_ON_CPU_HOST_PTR(p));
     }
 }
@@ -906,7 +906,7 @@  void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu,
             if (dst_cpu != src_cpu) {
                 TLBFlushRangeData *p = g_memdup(&d, sizeof(d));
                 async_run_on_cpu(dst_cpu,
-                                 tlb_flush_page_bits_by_mmuidx_async_2,
+                                 tlb_flush_range_by_mmuidx_async_1,
                                  RUN_ON_CPU_HOST_PTR(p));
             }
         }
@@ -964,13 +964,13 @@  void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
         CPU_FOREACH(dst_cpu) {
             if (dst_cpu != src_cpu) {
                 p = g_memdup(&d, sizeof(d));
-                async_run_on_cpu(dst_cpu, tlb_flush_page_bits_by_mmuidx_async_2,
+                async_run_on_cpu(dst_cpu, tlb_flush_range_by_mmuidx_async_1,
                                  RUN_ON_CPU_HOST_PTR(p));
             }
         }
 
         p = g_memdup(&d, sizeof(d));
-        async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_2,
+        async_safe_run_on_cpu(src_cpu, tlb_flush_range_by_mmuidx_async_1,
                               RUN_ON_CPU_HOST_PTR(p));
     }
 }