diff mbox

[[ARM/AArch64,testsuite] 13/36] Add vmla_n and vmls_n tests.

Message ID CAKdteOZaFDShT7juHGkuUHLz8bp-aHjL-bEvWCfrYr=tU5VgaA@mail.gmail.com
State Accepted
Commit a9f53b60f16ea7db457e996b039587fa0b2b6213
Headers show

Commit Message

Christophe Lyon Jan. 20, 2015, 3:28 p.m. UTC 
On 16 January 2015 at 17:24, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> +                                       0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>
>
> No poly vmlx_n, otherwise LGTM.
>
Here is a new version, with a bit more cleanup than requested, since
only 16x4 and 32x2 variants are supported.


> Tejas.
>
>
diff mbox

Patch

From 2b9d1ba0f54086dc6511766cbf19883b2439ca49 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Thu, 4 Dec 2014 00:37:35 +0100
Subject: [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests.


diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
new file mode 100644
index 0000000..375023a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
@@ -0,0 +1,87 @@ 
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+#define DECL_VMLX_N(VAR)			\
+  DECL_VARIABLE(VAR, int, 16, 4);		\
+  DECL_VARIABLE(VAR, int, 32, 2);		\
+  DECL_VARIABLE(VAR, uint, 16, 4);		\
+  DECL_VARIABLE(VAR, uint, 32, 2);		\
+  DECL_VARIABLE(VAR, float, 32, 2);		\
+  DECL_VARIABLE(VAR, int, 16, 8);		\
+  DECL_VARIABLE(VAR, int, 32, 4);		\
+  DECL_VARIABLE(VAR, uint, 16, 8);		\
+  DECL_VARIABLE(VAR, float, 32, 4);		\
+  DECL_VARIABLE(VAR, uint, 32, 4)
+
+  /* vector_res = vmlx_n(vector, vector2, val),
+     then store the result.  */
+#define TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V)          \
+  VECT_VAR(vector_res, T1, W, N) =                      \
+    INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N),     \
+			VECT_VAR(vector2, T1, W, N),    \
+			V);                             \
+  vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N),         \
+		    VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLX_N(INSN, Q, T1, T2, W, N, V)	\
+  TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V)
+
+  DECL_VMLX_N(vector);
+  DECL_VMLX_N(vector2);
+  DECL_VMLX_N(vector_res);
+
+  clean_results ();
+
+  VLOAD(vector, buffer, , int, s, 16, 4);
+  VLOAD(vector, buffer, , int, s, 32, 2);
+  VLOAD(vector, buffer, , uint, u, 16, 4);
+  VLOAD(vector, buffer, , uint, u, 32, 2);
+  VLOAD(vector, buffer, , float, f, 32, 2);
+  VLOAD(vector, buffer, q, int, s, 16, 8);
+  VLOAD(vector, buffer, q, int, s, 32, 4);
+  VLOAD(vector, buffer, q, uint, u, 16, 8);
+  VLOAD(vector, buffer, q, uint, u, 32, 4);
+  VLOAD(vector, buffer, q, float, f, 32, 4);
+
+  VDUP(vector2, , int, s, 16, 4, 0x55);
+  VDUP(vector2, , int, s, 32, 2, 0x55);
+  VDUP(vector2, , uint, u, 16, 4, 0x55);
+  VDUP(vector2, , uint, u, 32, 2, 0x55);
+  VDUP(vector2, , float, f, 32, 2, 55.2f);
+  VDUP(vector2, q, int, s, 16, 8, 0x55);
+  VDUP(vector2, q, int, s, 32, 4, 0x55);
+  VDUP(vector2, q, uint, u, 16, 8, 0x55);
+  VDUP(vector2, q, uint, u, 32, 4, 0x55);
+  VDUP(vector2, q, float, f, 32, 4, 55.9f);
+
+  /* Choose multiplier arbitrarily.  */
+  TEST_VMLX_N(INSN_NAME, , int, s, 16, 4, 0x11);
+  TEST_VMLX_N(INSN_NAME, , int, s, 32, 2, 0x22);
+  TEST_VMLX_N(INSN_NAME, , uint, u, 16, 4, 0x33);
+  TEST_VMLX_N(INSN_NAME, , uint, u, 32, 2, 0x44);
+  TEST_VMLX_N(INSN_NAME, , float, f, 32, 2, 22.3f);
+  TEST_VMLX_N(INSN_NAME, q, int, s, 16, 8, 0x55);
+  TEST_VMLX_N(INSN_NAME, q, int, s, 32, 4, 0x66);
+  TEST_VMLX_N(INSN_NAME, q, uint, u, 16, 8, 0x77);
+  TEST_VMLX_N(INSN_NAME, q, uint, u, 32, 4, 0x88);
+  TEST_VMLX_N(INSN_NAME, q, float, f, 32, 4, 66.7f);
+
+  CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+  CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+  CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+  CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+  CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+  CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+  CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+  CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+  CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+  CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int main (void)
+{
+  FNNAME (INSN_NAME) ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
new file mode 100644
index 0000000..8e88aad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
@@ -0,0 +1,23 @@ 
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmla
+#define TEST_MSG "VMLA_N"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x595, 0x596, 0x597, 0x598 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xb3a, 0xb3b };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1684, 0x1685 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4497deb8, 0x4497feb8 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x1c29, 0x1c2a, 0x1c2b, 0x1c2c,
+					0x1c2d, 0x1c2e, 0x1c2f, 0x1c30 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x21ce, 0x21cf, 0x21d0, 0x21d1 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x2773, 0x2774, 0x2775, 0x2776,
+					 0x2777, 0x2778, 0x2779, 0x277a };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x2d18, 0x2d19, 0x2d1a, 0x2d1b };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x4568087b, 0x4568187b,
+					   0x4568287b, 0x4568387b };
+
+#include "vmlX_n.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
new file mode 100644
index 0000000..228673b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
@@ -0,0 +1,25 @@ 
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmls
+#define TEST_MSG "VMLS_N"
+
+/* Expected results.  */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfa4b, 0xfa4c, 0xfa4d, 0xfa4e };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffff4a6, 0xfffff4a7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xef01, 0xef02, 0xef03, 0xef04 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffe95c, 0xffffe95d };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc49bdeb8, 0xc49bbeb8 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xe3b7, 0xe3b8, 0xe3b9, 0xe3ba,
+					0xe3bb, 0xe3bc, 0xe3bd, 0xe3be };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffde12, 0xffffde13,
+					0xffffde14, 0xffffde15 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xd86d, 0xd86e, 0xd86f, 0xd870,
+					 0xd871, 0xd872, 0xd873, 0xd874 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffd2c8, 0xffffd2c9,
+					 0xffffd2ca, 0xffffd2cb };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc56a087b, 0xc569f87b,
+					   0xc569e87b, 0xc569d87b };
+
+#include "vmlX_n.inc"
-- 
2.1.0