| Message ID | 20210512084724.14634-5-shruthi.sanil@intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Intel Keem Bay WDT bug fixes | expand |
On Wed, May 12, 2021 at 02:17:18PM +0530, shruthi.sanil@intel.com wrote: > From: Shruthi Sanil <shruthi.sanil@intel.com> > > During the interrupt service routine of the TimeOut interrupt and > the ThresHold interrupt, the respective interrupt clear bit > have to be cleared and not both. > > Fixes: fa0f8d51e90d ("watchdog: Add watchdog driver for Intel Keembay Soc") > Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Tested-by: Kris Pan <kris.pan@intel.com> > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/watchdog/keembay_wdt.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/watchdog/keembay_wdt.c b/drivers/watchdog/keembay_wdt.c > index 6053416b8d3d..f2a16c9933c3 100644 > --- a/drivers/watchdog/keembay_wdt.c > +++ b/drivers/watchdog/keembay_wdt.c > @@ -23,7 +23,8 @@ > #define TIM_WDOG_EN 0x8 > #define TIM_SAFE 0xc > > -#define WDT_ISR_MASK GENMASK(9, 8) > +#define WDT_TH_INT_MASK BIT(8) > +#define WDT_TO_INT_MASK BIT(9) > #define WDT_ISR_CLEAR 0x8200ff18 > #define WDT_UNLOCK 0xf1d0dead > #define WDT_LOAD_MAX U32_MAX > @@ -142,7 +143,7 @@ static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id) > struct arm_smccc_res res; > > keembay_wdt_writel(wdt, TIM_WATCHDOG, 1); > - arm_smccc_smc(WDT_ISR_CLEAR, WDT_ISR_MASK, 0, 0, 0, 0, 0, 0, &res); > + arm_smccc_smc(WDT_ISR_CLEAR, WDT_TO_INT_MASK, 0, 0, 0, 0, 0, 0, &res); > dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt timeout.\n"); > emergency_restart(); > > @@ -156,7 +157,7 @@ static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id) > > keembay_wdt_set_pretimeout(&wdt->wdd, 0x0); > > - arm_smccc_smc(WDT_ISR_CLEAR, WDT_ISR_MASK, 0, 0, 0, 0, 0, 0, &res); > + arm_smccc_smc(WDT_ISR_CLEAR, WDT_TH_INT_MASK, 0, 0, 0, 0, 0, 0, &res); > dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt pre-timeout.\n"); > watchdog_notify_pretimeout(&wdt->wdd); > > -- > 2.17.1 >
diff --git a/drivers/watchdog/keembay_wdt.c b/drivers/watchdog/keembay_wdt.c index 6053416b8d3d..f2a16c9933c3 100644 --- a/drivers/watchdog/keembay_wdt.c +++ b/drivers/watchdog/keembay_wdt.c @@ -23,7 +23,8 @@ #define TIM_WDOG_EN 0x8 #define TIM_SAFE 0xc -#define WDT_ISR_MASK GENMASK(9, 8) +#define WDT_TH_INT_MASK BIT(8) +#define WDT_TO_INT_MASK BIT(9) #define WDT_ISR_CLEAR 0x8200ff18 #define WDT_UNLOCK 0xf1d0dead #define WDT_LOAD_MAX U32_MAX @@ -142,7 +143,7 @@ static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id) struct arm_smccc_res res; keembay_wdt_writel(wdt, TIM_WATCHDOG, 1); - arm_smccc_smc(WDT_ISR_CLEAR, WDT_ISR_MASK, 0, 0, 0, 0, 0, 0, &res); + arm_smccc_smc(WDT_ISR_CLEAR, WDT_TO_INT_MASK, 0, 0, 0, 0, 0, 0, &res); dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt timeout.\n"); emergency_restart(); @@ -156,7 +157,7 @@ static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id) keembay_wdt_set_pretimeout(&wdt->wdd, 0x0); - arm_smccc_smc(WDT_ISR_CLEAR, WDT_ISR_MASK, 0, 0, 0, 0, 0, 0, &res); + arm_smccc_smc(WDT_ISR_CLEAR, WDT_TH_INT_MASK, 0, 0, 0, 0, 0, 0, &res); dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt pre-timeout.\n"); watchdog_notify_pretimeout(&wdt->wdd);