From patchwork Fri May 21 12:49:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 444680 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp947186jac; Fri, 21 May 2021 05:50:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxSr6oyHv4so24Gepzhf9VF5hAtJ+rewkHZT8iaOTU+Dc6j7L5d/VFpeItRu/YaoO+/zHy2 X-Received: by 2002:a62:5288:0:b029:2e3:fd7d:267a with SMTP id g130-20020a6252880000b02902e3fd7d267amr5895064pfb.21.1621601450983; Fri, 21 May 2021 05:50:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621601450; cv=none; d=google.com; s=arc-20160816; b=TZfC6ZlyZC3VXFmaX93ZgYVn7ExXCmU0XeAc6Ku3vGi7XDAn8SPCaS/+10zKh4H9eb NX9F3vjAV5ZZV4yol+y0Uc8UAjmoeuLQY7G8CmyHWLwAKtbX+zJQOhoNyiJ2fAW6WNSX VlnxBrMhAn2/ChpNuW9iWfMCePkZ49tsKF0SbxQph4ndrfKktrB3rRjWQiaPp0NQEyKG eENTx10GedATS91NwVD3eTN4bix9QYpnqPXjM8XM3kT/r1VKMAGuVxgigOQYgmXhCt14 IWV+oR5pAivUpLEOX7tWkuvVviyIy4oY40SP93ARN7LHUVp57JdP0eGLje5h+NCDhTtr 5F2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature:delivered-to; bh=O+21yLVLq+5P0fUEnFbXcir78ith8UdQJxVq7yONFUI=; b=DdzEkzWu/UhhDxVXgjuIvrLvtleHJXFlPYnnwYFioYeXU8AzjliME/QwF9o1u3jZDc 1zmSgttraUzUarlg2Th+xjVMQWWO6UKPHyObFyOhhLOf6lVa6UOwJe+iGbU2kY3yMgp2 MbBNbRmB5uM+cVIMiI36oSyB4/sV9uKCdlV3dKB7xsZ1Iem2eCl7YnMJBNugaMaJWW0r 2h10bCVjL/bOGcCVcHMsLyE84YKTNOGskYPfnVtQvS+k1mjSiwzujz7Q4VTohLgi/M3n crykOkcsXIoih1VjraH29ldxtuqztHjBb5Pcy+nAG6BI9L07ZFXt1w60eUWCPnEDlPle RM8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=p+b1dMuL; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id q21si7010987pfu.298.2021.05.21.05.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 May 2021 05:50:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=fail header.i=@kernel.org header.s=k20201202 header.b=p+b1dMuL; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C24686F641; Fri, 21 May 2021 12:50:49 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3902D6F640; Fri, 21 May 2021 12:50:48 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 4579D613D8; Fri, 21 May 2021 12:50:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621601448; bh=0XahmhIFMEbevuz651JK1SuRalOKFeJShM5ZS9hUNOw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p+b1dMuLcyV319Bhe3jSEigdayqKsFhF//ypqJCP+tluFH8ZmM8eq2gAlvlHrHLhG DM7rm48oYDW1OO42JBNc98oyZmjUCZwM3wiAVVBGBry1AAAwK7CK9NkoHxqmQGCbel MNp2RrXN7BjXR4PEqdURurAdn5zsJv5d5aUJzfjM/l2gHWboplc1+q3Bjl/4clH1tH 98w47KacMrvjiyAqlv4lewKUCj+5utIiFXscIPz/fBLWV/QsIeLUgEhp1WyMuaG60J L1vzriacLSu4IPLeYspBAA3IrFfoDsNdexO/Gii5yGjsCzMUzCLRjNeg5C/4/uPiQB cV3CdAQkUn3AQ== From: Vinod Koul To: Rob Clark Subject: [RFC PATCH 08/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl Date: Fri, 21 May 2021 18:19:40 +0530 Message-Id: <20210521124946.3617862-12-vkoul@kernel.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org> References: <20210521124946.3617862-1-vkoul@kernel.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , David Airlie , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Abhinav Kumar , Bjorn Andersson , Vinod Koul , dri-devel@lists.freedesktop.org, Dmitry Baryshkov , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Later gens of hardware have DSC bits moved to hw_ctl, so configure these bits so that DSC would work there as well Signed-off-by: Vinod Koul --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.26.3 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 2d4645e01ebf..aeea6add61ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -25,6 +25,8 @@ #define CTL_MERGE_3D_ACTIVE 0x0E4 #define CTL_INTF_ACTIVE 0x0F4 #define CTL_MERGE_3D_FLUSH 0x100 +#define CTL_DSC_ACTIVE 0x0E8 +#define CTL_DSC_FLUSH 0x104 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 #define CTL_FETCH_PIPE_ACTIVE 0x0FC @@ -34,6 +36,7 @@ #define DPU_REG_RESET_TIMEOUT_US 2000 #define MERGE_3D_IDX 23 +#define DSC_IDX 22 #define INTF_IDX 31 #define CTL_INVALID_BIT 0xffff @@ -120,6 +123,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3)); if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, @@ -128,7 +132,7 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH, ctx->pending_intf_flush_mask); - DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask | BIT(DSC_IDX)); } static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx) @@ -507,6 +511,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, BIT(0) | BIT(1) | BIT(2) | BIT(3)); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,