Message ID | 20210525055308.31069-3-steven_lee@aspeedtech.com |
---|---|
State | Superseded |
Headers | show |
Series | pinctrl: pinctrl-g6: Add the 2nd sgpio | expand |
On Tue, May 25, 2021 at 7:53 AM Steven Lee <steven_lee@aspeedtech.com> wrote: > AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces. > Currently, only SGPIO master 1 and SGPIO slve 1 in the pinctrl dtsi. > SGPIO master 2 and slave 2 should be added in pinctrl dtsi as well. > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Please funnel this patch through the Aspeed/ARM SoC tree. Yours, Linus Walleij
On Thu, 27 May 2021 at 23:47, Linus Walleij <linus.walleij@linaro.org> wrote: > > On Tue, May 25, 2021 at 7:53 AM Steven Lee <steven_lee@aspeedtech.com> wrote: > > > AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces. > > Currently, only SGPIO master 1 and SGPIO slve 1 in the pinctrl dtsi. > > SGPIO master 2 and slave 2 should be added in pinctrl dtsi as well. > > > > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> > > Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > Please funnel this patch through the Aspeed/ARM SoC tree. Applied, thanks.
diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 7028e21bdd98..7e90d713f5e5 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -862,11 +862,21 @@ groups = "SGPM1"; }; + pinctrl_sgpm2_default: sgpm2_default { + function = "SGPM2"; + groups = "SGPM2"; + }; + pinctrl_sgps1_default: sgps1_default { function = "SGPS1"; groups = "SGPS1"; }; + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; + pinctrl_sioonctrl_default: sioonctrl_default { function = "SIOONCTRL"; groups = "SIOONCTRL";