From patchwork Mon Jun 7 17:31:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 455436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56861C47082 for ; Mon, 7 Jun 2021 17:32:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 392FB610A8 for ; Mon, 7 Jun 2021 17:32:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231678AbhFGReH (ORCPT ); Mon, 7 Jun 2021 13:34:07 -0400 Received: from mail-dm6nam10on2073.outbound.protection.outlook.com ([40.107.93.73]:44170 "EHLO NAM10-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S231437AbhFGReC (ORCPT ); Mon, 7 Jun 2021 13:34:02 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eV5gRlzvNMSLepLpW6iwAeNRfIHhK4c1fN3OyOSIgcODNM+dvwaIU8tC0fULl7VFo4/ZvpC9ABAVudl9eT8Vu82IjGfkeep3n90S8FHh2IOiJdSTHsJlruv5hlH9Ry5B2MGHtrAS02dbmIpVzZd7o+ntfCpgSMkfTqL5dU10qcQGnaLhWc8o/WW+N0VL/1VfCTlZutnwtUBj8QUO8ny/77tflJFwqpI9Je1mKUFDFJDPFtgJm83HEA0apnX/A5h/Ado4hMV99eF5aoaLwxA+HZ9hH/pB2XPNTmhzWXKZBRdrCgBHGz4b1yt0q871rIhRyiTjq7OlFcEvxERgaujBCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bBprqBEisAm8e+59Dep1e/1Sn3f5I7vZQ89JahzIwu8=; b=QNDfgo11VkrFftCecp9C4nDz+vS0jFy+VLDil/gksfiOB+/RJiS9OIdGD7kZOlinnWpG27UeEOXlqZqiOZK8R1VhD6sfR9IRQjF65hmuxxnm78fVHeynmxdakiVKNhRTzFACI0pN8okPXC4Bv7gRCx7OqbyebfsEh/VB0EebqQDplNtEBgnY1ul0P713L0/Af+fDXhkdnO4Vc4RYVV71shX5C/EwE+dwV7Tnofk5QiXlwQfthA7KMWiGF75AEfR81OnVlrCcD5KnT87IBmudSnRUXrY0ttLmgIMNrqWSG6a+z3AInaljptu0t6+Ve/lGQ/+UzRbeGKQrh46cGBH/Dg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bBprqBEisAm8e+59Dep1e/1Sn3f5I7vZQ89JahzIwu8=; b=GTH/dkKzjfIAC9Nov7VZnkw3BwIkXLIsjV6jD6NltYz6TUot4ilYJwo209cg5RC1qq/Y9VwLlpc4vCGLj3v0PYl9n0ioFjqZbc87yzyp5RoTBRunO4VbRqx4nWLfuKe2EOZRHZx3R0KHVSwWouTf7JAoab/OsUCTIPC+k6ydLHQ= Authentication-Results: kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=amd.com; Received: from SA0PR12MB4510.namprd12.prod.outlook.com (2603:10b6:806:94::8) by SA0PR12MB4510.namprd12.prod.outlook.com (2603:10b6:806:94::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.24; Mon, 7 Jun 2021 17:32:08 +0000 Received: from SA0PR12MB4510.namprd12.prod.outlook.com ([fe80::d51c:6137:77f2:5671]) by SA0PR12MB4510.namprd12.prod.outlook.com ([fe80::d51c:6137:77f2:5671%4]) with mapi id 15.20.4195.030; Mon, 7 Jun 2021 17:32:08 +0000 From: Mario Limonciello To: Keith Busch , Jens Axboe , Christoph Hellwig , Sagi Grimberg , "Rafael J . Wysocki" Cc: linux-nvme@lists.infradead.org (open list:NVM EXPRESS DRIVER), linux-acpi@vger.kernel.org, rrangel@chromium.org, david.e.box@linux.intel.com, Shyam-sundar.S-k@amd.com, Nehal-bakulchandra.Shah@amd.com, Alexander.Deucher@amd.com, prike.liang@amd.com, Mario Limonciello , Julian Sikorski Subject: [PATCH v6 2/2] ACPI: Add quirks for AMD Renoir/Lucienne CPUs to force the D3 hint Date: Mon, 7 Jun 2021 12:31:56 -0500 Message-Id: <20210607173156.5548-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210607173156.5548-1-mario.limonciello@amd.com> References: <20210607173156.5548-1-mario.limonciello@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN7PR04CA0162.namprd04.prod.outlook.com (2603:10b6:806:125::17) To SA0PR12MB4510.namprd12.prod.outlook.com (2603:10b6:806:94::8) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from AUS-LX-MLIMONCI.amd.com (165.204.77.1) by SN7PR04CA0162.namprd04.prod.outlook.com (2603:10b6:806:125::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.20 via Frontend Transport; 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This is "typically" accomplished using the `StorageD3Enable` property in the _DSD, but this property was introduced after many of these systems launched and most OEM systems don't have it in their BIOS. On AMD Renoir without these drives going into D3 over suspend-to-idle the resume will fail with the NVME controller being reset and a trace like this in the kernel logs: ``` [ 83.556118] nvme nvme0: I/O 161 QID 2 timeout, aborting [ 83.556178] nvme nvme0: I/O 162 QID 2 timeout, aborting [ 83.556187] nvme nvme0: I/O 163 QID 2 timeout, aborting [ 83.556196] nvme nvme0: I/O 164 QID 2 timeout, aborting [ 95.332114] nvme nvme0: I/O 25 QID 0 timeout, reset controller [ 95.332843] nvme nvme0: Abort status: 0x371 [ 95.332852] nvme nvme0: Abort status: 0x371 [ 95.332856] nvme nvme0: Abort status: 0x371 [ 95.332859] nvme nvme0: Abort status: 0x371 [ 95.332909] PM: dpm_run_callback(): pci_pm_resume+0x0/0xe0 returns -16 [ 95.332936] nvme 0000:03:00.0: PM: failed to resume async: error -16 ``` The Microsoft documentation for StorageD3Enable mentioned that Windows has a hardcoded allowlist for D3 support, which was used for these platforms. Introduce quirks to hardcode them for Linux as well. As this property is now "standardized", OEM systems using AMD Cezanne and newer APU's have adopted this property, and quirks like this should not be necessary. CC: Julian Sikorski CC: Shyam-sundar S-k CC: Alexander Deucher CC: Rafael J. Wysocki CC: Prike Liang Link: https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro Signed-off-by: Mario Limonciello Tested-by: Julian Sikorski --- drivers/acpi/device_pm.c | 3 +++ drivers/acpi/x86/utils.c | 27 +++++++++++++++++++++++++++ include/acpi/acpi_bus.h | 5 +++++ 3 files changed, 35 insertions(+) Changes from v4->v5: * Add this patch back in as it's been made apparent that the system needs to be hardcoded for these. Changes: - Drop Cezanne - it's now covered by StorageD3Enable - Rebase ontop of acpi_storage_d3 outside of NVME Changes from v5->v6: * Move the quirk check into drivers/acpi/x86/ as suggested by Rafael. diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c index 1edb68d00b8e..985c17384192 100644 --- a/drivers/acpi/device_pm.c +++ b/drivers/acpi/device_pm.c @@ -1356,6 +1356,9 @@ bool acpi_storage_d3(struct device *dev) struct acpi_device *adev = ACPI_COMPANION(dev); u8 val; + if (force_storage_d3()) + return true; + if (!adev) return false; if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable", diff --git a/drivers/acpi/x86/utils.c b/drivers/acpi/x86/utils.c index bdc1ba00aee9..2b8d5b3c876f 100644 --- a/drivers/acpi/x86/utils.c +++ b/drivers/acpi/x86/utils.c @@ -135,3 +135,30 @@ bool acpi_device_always_present(struct acpi_device *adev) return ret; } + +/* + * AMD systems from Renoir and Lucienne *require* that the NVME controller + * is put into D3 over a Modern Standby / suspend-to-idle cycle. + * + * This is "typically" accomplished using the `StorageD3Enable` + * property in the _DSD that is checked via the `acpi_storage_d3` function + * but this property was introduced after many of these systems launched + * and most OEM systems don't have it in their BIOS. + * + * The Microsoft documentation for StorageD3Enable mentioned that Windows has + * a hardcoded allowlist for D3 support, which was used for these platforms. + * + * This allows quirking on Linux in a similar fashion. + */ +const struct x86_cpu_id storage_d3_cpu_ids[] = { + X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL), /* Renoir */ + X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104, NULL), /* Lucienne */ + {} +}; + +bool force_storage_d3(void) +{ + if (x86_match_cpu(storage_d3_cpu_ids)) + return true; + return false; +} diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 3a82faac5767..9b0ddbae5617 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -607,11 +607,16 @@ int acpi_disable_wakeup_device_power(struct acpi_device *dev); #ifdef CONFIG_X86 bool acpi_device_always_present(struct acpi_device *adev); +bool force_storage_d3(void); #else static inline bool acpi_device_always_present(struct acpi_device *adev) { return false; } +static inline bool force_storage_d3(void) +{ + return false; +} #endif #ifdef CONFIG_PM