@@ -3646,6 +3646,24 @@ swm: swm@c85 {
};
};
+ lmh_cluster1: lmh@17d70800 {
+ compatible = "qcom,msm-hw-limits";
+ reg = <0 0x17d70800 0 0x401>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,lmh-cpu-id = <0x4>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ lmh_cluster0: lmh@17d78800 {
+ compatible = "qcom,msm-hw-limits";
+ reg = <0 0x17d78800 0 0x401>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,lmh-cpu-id = <0x0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
sound: sound {
};
@@ -4911,10 +4929,13 @@ cpufreq_hw: cpufreq@17d43000 {
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
+ interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
+
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
+ qcom,support-lmh = <1>;
};
wifi: wifi@18800000 {
Add LMh nodes for cpu cluster0 and cpu cluster1. Also add interrupt support in cpufreq node to capture the LMh interrupt and let the scheduler know of the max frequency throttling. Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)