| Message ID | 20210613094639.3242151-1-mnhagan88@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/4] ARM: dts: NSP: disable qspi node by default | expand |
On 13/06/2021 17:22, Florian Fainelli wrote: > > On 6/13/2021 2:46 AM, Matthew Hagan wrote: >> The sp804 ccbtimers are enabled by default, however they may or may not >> be present on the board. This patch disables them by default, requiring >> them to be enabled only where applicable. > The timers are always part of the SoC, so they should always be enabled, > and if there was some board specific wiring, in that maybe one of the > times was fed a different clock source than iprocslow, we could deal > with that on a per-board basis. > > If someone does not want a specific timer to be used, it could be > unbound once the kernel has booted for instance. I should have spent more time to look at the issue rather rather than proposing to disable parts of the SoC. In my case with ccbtimer0, ccbtimer1 both enabled: [ 0.000181] clocksource: arm,sp804: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 15290083572 ns [ 0.000209] Failed to initialize '/axi@18000000/timer@35000': -22 but with ccbtimer0 disabled, ccbtimer1 now initialises correctly: [ 0.000186] clocksource: arm,sp804: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 15290083572 ns Will investigate this further, but yes this patch should be dropped. Thanks, Matthew
On Sun, 13 Jun 2021 10:46:34 +0100, Matthew Hagan <mnhagan88@gmail.com> wrote: > The QSPI bus is enabled by default, however this may not used on all > devices. This patch disables by default, requiring it to be explicitly > enabled where required. > > Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> > --- Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! -- Florian
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index b4d2cc70afb1..c0427d985438 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -310,6 +310,7 @@ qspi: spi@27200 { num-cs = <2>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; xhci: usb@29000 { diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index b6f4d931123c..e5ed67b3c35f 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -134,6 +134,7 @@ nand_sel: nand_sel { }; &qspi { + status = "okay"; bspi-sel = <0>; flash: m25p80@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index af66caa87bfc..017fc46cdf0b 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -134,6 +134,7 @@ nand_sel: nand_sel { }; &qspi { + status = "okay"; bspi-sel = <0>; flash: m25p80@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index 3d6859e4fd5e..5364f98ae1b8 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -150,6 +150,7 @@ nand_sel: nand_sel { }; &qspi { + status = "okay"; bspi-sel = <0>; flash: m25p80@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index dca2c9c60857..4763eb5d68a6 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -138,6 +138,7 @@ nand_sel: nand_sel { }; &qspi { + status = "okay"; bspi-sel = <0>; flash: m25p80@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index 4e106ce1384a..f2468bed2808 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -142,6 +142,7 @@ &sata_phy0 { }; &qspi { + status = "okay"; bspi-sel = <0>; flash: m25p80@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index 3a62d2d90a18..c26849304bc7 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -149,6 +149,7 @@ nand_sel: nand_sel { }; &qspi { + status = "okay"; bspi-sel = <0>; flash: m25p80@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index d331c0a4e6b6..b7b136c862a8 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -153,6 +153,7 @@ &pwm { }; &qspi { + status = "okay"; bspi-sel = <0>; flash: m25p80@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index 7cfb48fb48ba..6b57530a3964 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -138,6 +138,7 @@ nand_sel: nand_sel { }; &qspi { + status = "okay"; bspi-sel = <0>; flash: m25p80@0 { #address-cells = <1>;
The QSPI bus is enabled by default, however this may not used on all devices. This patch disables by default, requiring it to be explicitly enabled where required. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> --- arch/arm/boot/dts/bcm-nsp.dtsi | 1 + arch/arm/boot/dts/bcm958522er.dts | 1 + arch/arm/boot/dts/bcm958525er.dts | 1 + arch/arm/boot/dts/bcm958525xmc.dts | 1 + arch/arm/boot/dts/bcm958622hr.dts | 1 + arch/arm/boot/dts/bcm958623hr.dts | 1 + arch/arm/boot/dts/bcm958625hr.dts | 1 + arch/arm/boot/dts/bcm958625k.dts | 1 + arch/arm/boot/dts/bcm988312hr.dts | 1 + 9 files changed, 9 insertions(+)