| Message ID | 1623835059-29302-1-git-send-email-sbhanu@codeaurora.org |
|---|---|
| State | New |
| Headers | show |
| Series | [V2] arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card | expand |
On Wed 16 Jun 04:17 CDT 2021, Shaik Sajida Bhanu wrote: > Add XO clock for eMMC and SDCard as it would help in calculating dll > register values. > > Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > > Changes since V1: > - Updated commit message as suggested by Bjorn Andersson. > - Added space after before xo clock name as suggested by > Konrad Dybcio. Thank you Shaik. Sorry if I wasn't clear when I tried to say that I fixed these things and applied your previous patch. Regards, Bjorn > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 52115e0..fb1d9ad 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -701,8 +701,9 @@ > interrupt-names = "hc_irq", "pwr_irq"; > > clocks = <&gcc GCC_SDCC1_APPS_CLK>, > - <&gcc GCC_SDCC1_AHB_CLK>; > - clock-names = "core", "iface"; > + <&gcc GCC_SDCC1_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "core", "iface", "xo"; > interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; > interconnect-names = "sdhc-ddr","cpu-sdhc"; > @@ -2564,8 +2565,9 @@ > interrupt-names = "hc_irq", "pwr_irq"; > > clocks = <&gcc GCC_SDCC2_APPS_CLK>, > - <&gcc GCC_SDCC2_AHB_CLK>; > - clock-names = "core", "iface"; > + <&gcc GCC_SDCC2_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "core", "iface", "xo"; > > interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 52115e0..fb1d9ad 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -701,8 +701,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -2564,8 +2565,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;