diff mbox series

[RFC,v1,152/256] cl8k: add reg/reg_fem.h

Message ID 20210617160223.160998-153-viktor.barna@celeno.com
State New
Headers show
Series wireless: cl8k driver for Celeno IEEE 802.11ax devices | expand

Commit Message

Viktor Barna June 17, 2021, 4 p.m. UTC 
From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 .../net/wireless/celeno/cl8k/reg/reg_fem.h    | 102 ++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_fem.h

--
2.30.0
diff mbox series

Patch

diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_fem.h b/drivers/net/wireless/celeno/cl8k/reg/reg_fem.h
new file mode 100644
index 000000000000..ab1aaae23782
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_fem.h
@@ -0,0 +1,102 @@ 
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_FEM_H
+#define CL_REG_FEM_H
+
+#include "reg/reg_io_ctrl.h"
+
+struct cl_fem_lna_enable_gpio {
+       union {
+               u16 b0 : 1,
+                   b1 : 1,
+                   b2 : 1,
+                   b3 : 1,
+                   b4 : 1,
+                   b5 : 1,
+                   b6 : 1,
+                   b7 : 1,
+                   b8 : 1,
+                   b9 : 1,
+                   b10 : 1,
+                   b11 : 1,
+                   rsv : 4;
+               u16 val;
+       };
+};
+
+struct cl_fem_pa_enable_gpio {
+       union {
+               u16 b0 : 1,
+                   b1 : 1,
+                   b2 : 1,
+                   b3 : 1,
+                   b4 : 1,
+                   b5 : 1,
+                   b6 : 1,
+                   b7 : 1,
+                   b8 : 1,
+                   b9 : 1,
+                   b10 : 1,
+                   b11 : 1,
+                   rsv : 4;
+               u16 val;
+       };
+};
+
+struct cl_fem_rx_active_gpio {
+       union {
+               u8 b0 : 1,
+                  b1 : 1,
+                  b2 : 1,
+                  b3 : 1,
+                  b4 : 1,
+                  b5 : 1,
+                  b6 : 1,
+                  b7 : 1;
+               u8 val;
+       };
+};
+
+#define EXTRACT_OFF_LUT(lut) (((lut) >> 12) & 0x7)
+#define FEM_LUT_MASK         0x0777
+
+#define PA_ENABLE_POS  0
+#define LNA_ENABLE_POS 1
+#define RX_ACTIVE_POS  2
+#define GET_BIT(reg, pos) (((reg) >> (pos)) & 0x1)
+
+/*
+ * LNA_ENABLE
+ * IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_POS is used for all ioctl APIs -
+ * io_ctrl_lna_enable_0_set() ... io_ctrl_lna_enable_11_set()
+ * because all have the same value
+ */
+#define LNA_ENABLE_GPIO_VAL(val) \
+       (((u32)(val) << IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_POS) & \
+        IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_BIT)
+
+/* PA_ENABLE */
+#define PA_ENABLE_GPIO_VAL(val) \
+       (((u32)(val) << IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_POS) & \
+        IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_BIT)
+
+/* RX_ACTIVE */
+#define RX_ACTIVE_GPIO_VAL(val) \
+       (((u32)(val) << IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_POS) & \
+        IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_BIT)
+
+#define LNA_ENABLE_GPIO_OUT_CFG(val) \
+       (((1 << IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_POS) & IO_CTRL_LNA_ENABLE_0_GPIO_ENABLE_BIT) | \
+        ((1 << IO_CTRL_LNA_ENABLE_0_GPIO_OE_POS) & IO_CTRL_LNA_ENABLE_0_GPIO_OE_BIT) | \
+        (((u32)(val) << IO_CTRL_LNA_ENABLE_0_GPIO_OUT_POS) & IO_CTRL_LNA_ENABLE_0_GPIO_OUT_BIT))
+#define PA_ENABLE_GPIO_OUT_CFG(val) \
+        (((1 << IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_POS) & IO_CTRL_PA_ENABLE_0_GPIO_ENABLE_BIT) | \
+         ((1 << IO_CTRL_PA_ENABLE_0_GPIO_OE_POS) & IO_CTRL_PA_ENABLE_0_GPIO_OE_BIT) | \
+         (((u32)(val) << IO_CTRL_PA_ENABLE_0_GPIO_OUT_POS) & IO_CTRL_PA_ENABLE_0_GPIO_OUT_BIT))
+#define RX_ACTIVE_GPIO_OUT_CFG(val) \
+         (((1 << IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_POS) & IO_CTRL_RX_ACTIVE_0_GPIO_ENABLE_BIT) | \
+          ((1 << IO_CTRL_RX_ACTIVE_0_GPIO_OE_POS) & IO_CTRL_RX_ACTIVE_0_GPIO_OE_BIT) | \
+          (((u32)(val) << IO_CTRL_RX_ACTIVE_0_GPIO_OUT_POS) & IO_CTRL_RX_ACTIVE_0_GPIO_OUT_BIT))
+
+#endif /* CL_REG_FEM_H */