Message ID | 20210618123851.1344518-12-anup.patel@wdc.com |
---|---|
State | Superseded |
Headers | show
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Fri, 18 Jun 2021 12:40:05 +0000 From: Anup Patel <anup.patel@wdc.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Palmer Dabbelt <palmerdabbelt@google.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Rob Herring <robh+dt@kernel.org> Cc: Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>, Bin Meng <bmeng.cn@gmail.com> Subject: [RFC PATCH v2 11/11] MAINTAINERS: Add entry for RISC-V ACLINT drivers Date: Fri, 18 Jun 2021 18:08:51 +0530 Message-Id: <20210618123851.1344518-12-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210618123851.1344518-1-anup.patel@wdc.com> References: <20210618123851.1344518-1-anup.patel@wdc.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [122.171.164.186] X-ClientProxiedBy: MA1PR0101CA0025.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::11) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.171.164.186) by MA1PR0101CA0025.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.15 via Frontend Transport; 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Linux RISC-V ACLINT Support
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diff --git a/MAINTAINERS b/MAINTAINERS index bc0ceef87b73..64a5ee2fb20c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15693,6 +15693,15 @@ S: Maintained F: drivers/mtd/nand/raw/r852.c F: drivers/mtd/nand/raw/r852.h +RISC-V ACLINT DRIVERS +M: Anup Patel <anup.patel@wdc.com> +L: linux-riscv@lists.infradead.org +S: Supported +F: Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml +F: Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml +F: drivers/clocksource/timer-clint.c +F: drivers/irqchip/irq-aclint-swi.c + RISC-V ARCHITECTURE M: Paul Walmsley <paul.walmsley@sifive.com> M: Palmer Dabbelt <palmer@dabbelt.com>