[v2,02/10] target/ppc: Use MMUAccessType with *_handle_mmu_fault

Message ID 20210621125115.67717-3-bruno.larsen@eldorado.org.br
State New
Headers show
Series
  • [v2,01/10] target/ppc: Remove PowerPCCPUClass.handle_mmu_fault
Related show

Commit Message

Bruno Piazera Larsen June 21, 2021, 12:51 p.m.
From: Richard Henderson <richard.henderson@linaro.org>


These changes were waiting until we didn't need to match
the function type of PowerPCCPUClass.handle_mmu_fault.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/ppc/mmu-hash32.c  | 7 ++-----
 target/ppc/mmu-hash32.h  | 4 ++--
 target/ppc/mmu-hash64.c  | 6 +-----
 target/ppc/mmu-hash64.h  | 4 ++--
 target/ppc/mmu-radix64.c | 7 ++-----
 target/ppc/mmu-radix64.h | 4 ++--
 6 files changed, 11 insertions(+), 21 deletions(-)

-- 
2.17.1

Comments

Greg Kurz June 22, 2021, 12:05 p.m. | #1
On Mon, 21 Jun 2021 09:51:07 -0300
"Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br> wrote:

> From: Richard Henderson <richard.henderson@linaro.org>

> 

> These changes were waiting until we didn't need to match

> the function type of PowerPCCPUClass.handle_mmu_fault.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---


Reviewed-by: Greg Kurz <groug@kaod.org>


>  target/ppc/mmu-hash32.c  | 7 ++-----

>  target/ppc/mmu-hash32.h  | 4 ++--

>  target/ppc/mmu-hash64.c  | 6 +-----

>  target/ppc/mmu-hash64.h  | 4 ++--

>  target/ppc/mmu-radix64.c | 7 ++-----

>  target/ppc/mmu-radix64.h | 4 ++--

>  6 files changed, 11 insertions(+), 21 deletions(-)

> 

> diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c

> index 9f0a497657..8f19b43e47 100644

> --- a/target/ppc/mmu-hash32.c

> +++ b/target/ppc/mmu-hash32.c

> @@ -415,8 +415,8 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,

>      return (rpn & ~mask) | (eaddr & mask);

>  }

>  

> -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,

> -                                int mmu_idx)

> +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

> +                                MMUAccessType access_type, int mmu_idx)

>  {

>      CPUState *cs = CPU(cpu);

>      CPUPPCState *env = &cpu->env;

> @@ -425,11 +425,8 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,

>      ppc_hash_pte32_t pte;

>      int prot;

>      int need_prot;

> -    MMUAccessType access_type;

>      hwaddr raddr;

>  

> -    assert((rwx == 0) || (rwx == 1) || (rwx == 2));

> -    access_type = rwx;

>      need_prot = prot_for_access_type(access_type);

>  

>      /* 1. Handle real mode accesses */

> diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h

> index 898021f0d8..30e35718a7 100644

> --- a/target/ppc/mmu-hash32.h

> +++ b/target/ppc/mmu-hash32.h

> @@ -5,8 +5,8 @@

>  

>  hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash);

>  hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);

> -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,

> -                                int mmu_idx);

> +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address,

> +                                MMUAccessType access_type, int mmu_idx);

>  

>  /*

>   * Segment register definitions

> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c

> index 708dffc31b..2febd369b1 100644

> --- a/target/ppc/mmu-hash64.c

> +++ b/target/ppc/mmu-hash64.c

> @@ -874,7 +874,7 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)

>  }

>  

>  int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

> -                                int rwx, int mmu_idx)

> +                                MMUAccessType access_type, int mmu_idx)

>  {

>      CPUState *cs = CPU(cpu);

>      CPUPPCState *env = &cpu->env;

> @@ -884,13 +884,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

>      hwaddr ptex;

>      ppc_hash_pte64_t pte;

>      int exec_prot, pp_prot, amr_prot, prot;

> -    MMUAccessType access_type;

>      int need_prot;

>      hwaddr raddr;

>  

> -    assert((rwx == 0) || (rwx == 1) || (rwx == 2));

> -    access_type = rwx;

> -

>      /*

>       * Note on LPCR usage: 970 uses HID4, but our special variant of

>       * store_spr copies relevant fields into env->spr[SPR_LPCR].

> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h

> index 4b8b8e7950..3e8a8eec1f 100644

> --- a/target/ppc/mmu-hash64.h

> +++ b/target/ppc/mmu-hash64.h

> @@ -8,8 +8,8 @@ void dump_slb(PowerPCCPU *cpu);

>  int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,

>                    target_ulong esid, target_ulong vsid);

>  hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);

> -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,

> -                                int mmu_idx);

> +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address,

> +                                MMUAccessType access_type, int mmu_idx);

>  void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,

>                                 target_ulong pte_index,

>                                 target_ulong pte0, target_ulong pte1);

> diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c

> index b6d191c1d8..1c707d387d 100644

> --- a/target/ppc/mmu-radix64.c

> +++ b/target/ppc/mmu-radix64.c

> @@ -555,19 +555,16 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,

>      return 0;

>  }

>  

> -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,

> -                                 int mmu_idx)

> +int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

> +                                 MMUAccessType access_type, int mmu_idx)

>  {

>      CPUState *cs = CPU(cpu);

>      CPUPPCState *env = &cpu->env;

>      int page_size, prot;

>      bool relocation;

> -    MMUAccessType access_type;

>      hwaddr raddr;

>  

>      assert(!(msr_hv && cpu->vhyp));

> -    assert((rwx == 0) || (rwx == 1) || (rwx == 2));

> -    access_type = rwx;

>  

>      relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);

>      /* HV or virtual hypervisor Real Mode Access */

> diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h

> index f28c5794d0..94bd72cb38 100644

> --- a/target/ppc/mmu-radix64.h

> +++ b/target/ppc/mmu-radix64.h

> @@ -44,8 +44,8 @@

>  

>  #ifdef TARGET_PPC64

>  

> -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,

> -                                 int mmu_idx);

> +int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

> +                                 MMUAccessType access_type, int mmu_idx);

>  hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);

>  

>  static inline int ppc_radix64_get_prot_eaa(uint64_t pte)
David Gibson June 24, 2021, 3:19 a.m. | #2
On Mon, Jun 21, 2021 at 09:51:07AM -0300, Bruno Larsen (billionai) wrote:
> From: Richard Henderson <richard.henderson@linaro.org>

> 

> These changes were waiting until we didn't need to match

> the function type of PowerPCCPUClass.handle_mmu_fault.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Applied to ppc-for-6.1, thanks.

> ---

>  target/ppc/mmu-hash32.c  | 7 ++-----

>  target/ppc/mmu-hash32.h  | 4 ++--

>  target/ppc/mmu-hash64.c  | 6 +-----

>  target/ppc/mmu-hash64.h  | 4 ++--

>  target/ppc/mmu-radix64.c | 7 ++-----

>  target/ppc/mmu-radix64.h | 4 ++--

>  6 files changed, 11 insertions(+), 21 deletions(-)

> 

> diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c

> index 9f0a497657..8f19b43e47 100644

> --- a/target/ppc/mmu-hash32.c

> +++ b/target/ppc/mmu-hash32.c

> @@ -415,8 +415,8 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,

>      return (rpn & ~mask) | (eaddr & mask);

>  }

>  

> -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,

> -                                int mmu_idx)

> +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

> +                                MMUAccessType access_type, int mmu_idx)

>  {

>      CPUState *cs = CPU(cpu);

>      CPUPPCState *env = &cpu->env;

> @@ -425,11 +425,8 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,

>      ppc_hash_pte32_t pte;

>      int prot;

>      int need_prot;

> -    MMUAccessType access_type;

>      hwaddr raddr;

>  

> -    assert((rwx == 0) || (rwx == 1) || (rwx == 2));

> -    access_type = rwx;

>      need_prot = prot_for_access_type(access_type);

>  

>      /* 1. Handle real mode accesses */

> diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h

> index 898021f0d8..30e35718a7 100644

> --- a/target/ppc/mmu-hash32.h

> +++ b/target/ppc/mmu-hash32.h

> @@ -5,8 +5,8 @@

>  

>  hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash);

>  hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);

> -int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,

> -                                int mmu_idx);

> +int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address,

> +                                MMUAccessType access_type, int mmu_idx);

>  

>  /*

>   * Segment register definitions

> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c

> index 708dffc31b..2febd369b1 100644

> --- a/target/ppc/mmu-hash64.c

> +++ b/target/ppc/mmu-hash64.c

> @@ -874,7 +874,7 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)

>  }

>  

>  int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

> -                                int rwx, int mmu_idx)

> +                                MMUAccessType access_type, int mmu_idx)

>  {

>      CPUState *cs = CPU(cpu);

>      CPUPPCState *env = &cpu->env;

> @@ -884,13 +884,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

>      hwaddr ptex;

>      ppc_hash_pte64_t pte;

>      int exec_prot, pp_prot, amr_prot, prot;

> -    MMUAccessType access_type;

>      int need_prot;

>      hwaddr raddr;

>  

> -    assert((rwx == 0) || (rwx == 1) || (rwx == 2));

> -    access_type = rwx;

> -

>      /*

>       * Note on LPCR usage: 970 uses HID4, but our special variant of

>       * store_spr copies relevant fields into env->spr[SPR_LPCR].

> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h

> index 4b8b8e7950..3e8a8eec1f 100644

> --- a/target/ppc/mmu-hash64.h

> +++ b/target/ppc/mmu-hash64.h

> @@ -8,8 +8,8 @@ void dump_slb(PowerPCCPU *cpu);

>  int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,

>                    target_ulong esid, target_ulong vsid);

>  hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);

> -int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,

> -                                int mmu_idx);

> +int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address,

> +                                MMUAccessType access_type, int mmu_idx);

>  void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,

>                                 target_ulong pte_index,

>                                 target_ulong pte0, target_ulong pte1);

> diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c

> index b6d191c1d8..1c707d387d 100644

> --- a/target/ppc/mmu-radix64.c

> +++ b/target/ppc/mmu-radix64.c

> @@ -555,19 +555,16 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,

>      return 0;

>  }

>  

> -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,

> -                                 int mmu_idx)

> +int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

> +                                 MMUAccessType access_type, int mmu_idx)

>  {

>      CPUState *cs = CPU(cpu);

>      CPUPPCState *env = &cpu->env;

>      int page_size, prot;

>      bool relocation;

> -    MMUAccessType access_type;

>      hwaddr raddr;

>  

>      assert(!(msr_hv && cpu->vhyp));

> -    assert((rwx == 0) || (rwx == 1) || (rwx == 2));

> -    access_type = rwx;

>  

>      relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);

>      /* HV or virtual hypervisor Real Mode Access */

> diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h

> index f28c5794d0..94bd72cb38 100644

> --- a/target/ppc/mmu-radix64.h

> +++ b/target/ppc/mmu-radix64.h

> @@ -44,8 +44,8 @@

>  

>  #ifdef TARGET_PPC64

>  

> -int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,

> -                                 int mmu_idx);

> +int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,

> +                                 MMUAccessType access_type, int mmu_idx);

>  hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);

>  

>  static inline int ppc_radix64_get_prot_eaa(uint64_t pte)


-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Patch

diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index 9f0a497657..8f19b43e47 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -415,8 +415,8 @@  static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
     return (rpn & ~mask) | (eaddr & mask);
 }
 
-int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
-                                int mmu_idx)
+int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
+                                MMUAccessType access_type, int mmu_idx)
 {
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
@@ -425,11 +425,8 @@  int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
     ppc_hash_pte32_t pte;
     int prot;
     int need_prot;
-    MMUAccessType access_type;
     hwaddr raddr;
 
-    assert((rwx == 0) || (rwx == 1) || (rwx == 2));
-    access_type = rwx;
     need_prot = prot_for_access_type(access_type);
 
     /* 1. Handle real mode accesses */
diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h
index 898021f0d8..30e35718a7 100644
--- a/target/ppc/mmu-hash32.h
+++ b/target/ppc/mmu-hash32.h
@@ -5,8 +5,8 @@ 
 
 hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash);
 hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
-int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,
-                                int mmu_idx);
+int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address,
+                                MMUAccessType access_type, int mmu_idx);
 
 /*
  * Segment register definitions
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 708dffc31b..2febd369b1 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -874,7 +874,7 @@  static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
 }
 
 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
-                                int rwx, int mmu_idx)
+                                MMUAccessType access_type, int mmu_idx)
 {
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
@@ -884,13 +884,9 @@  int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
     hwaddr ptex;
     ppc_hash_pte64_t pte;
     int exec_prot, pp_prot, amr_prot, prot;
-    MMUAccessType access_type;
     int need_prot;
     hwaddr raddr;
 
-    assert((rwx == 0) || (rwx == 1) || (rwx == 2));
-    access_type = rwx;
-
     /*
      * Note on LPCR usage: 970 uses HID4, but our special variant of
      * store_spr copies relevant fields into env->spr[SPR_LPCR].
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 4b8b8e7950..3e8a8eec1f 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -8,8 +8,8 @@  void dump_slb(PowerPCCPU *cpu);
 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
                   target_ulong esid, target_ulong vsid);
 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
-int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,
-                                int mmu_idx);
+int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address,
+                                MMUAccessType access_type, int mmu_idx);
 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
                                target_ulong pte_index,
                                target_ulong pte0, target_ulong pte1);
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index b6d191c1d8..1c707d387d 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -555,19 +555,16 @@  static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr,
     return 0;
 }
 
-int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
-                                 int mmu_idx)
+int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
+                                 MMUAccessType access_type, int mmu_idx)
 {
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
     int page_size, prot;
     bool relocation;
-    MMUAccessType access_type;
     hwaddr raddr;
 
     assert(!(msr_hv && cpu->vhyp));
-    assert((rwx == 0) || (rwx == 1) || (rwx == 2));
-    access_type = rwx;
 
     relocation = (access_type == MMU_INST_FETCH ? msr_ir : msr_dr);
     /* HV or virtual hypervisor Real Mode Access */
diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h
index f28c5794d0..94bd72cb38 100644
--- a/target/ppc/mmu-radix64.h
+++ b/target/ppc/mmu-radix64.h
@@ -44,8 +44,8 @@ 
 
 #ifdef TARGET_PPC64
 
-int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
-                                 int mmu_idx);
+int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
+                                 MMUAccessType access_type, int mmu_idx);
 hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
 
 static inline int ppc_radix64_get_prot_eaa(uint64_t pte)