From patchwork Mon Jun 21 16:27:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 464545 Delivered-To: patch@linaro.org Received: by 2002:a17:906:71d0:0:0:0:0 with SMTP id i16csp4370397ejk; Mon, 21 Jun 2021 09:38:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJysyrRzE5HEHfG2ZkYFauu7wvgJ2fATyRWbesHPAADWhWFzWezaaHWphUJelRd6kHnEWTWJ X-Received: by 2002:a05:6402:1145:: with SMTP id g5mr22420663edw.217.1624293498651; Mon, 21 Jun 2021 09:38:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624293498; cv=none; d=google.com; s=arc-20160816; b=Pi24C/bOG2/VKynl/O5z7QK0FLW2+bc5L2u+8Qr8t9n1pRhc/Kb7iI6f2/i0ET0X/e /s6Oksit3ew5+MFuP8XpP3aButjOKhniHsYZDyvmr6Z63SEWN+P3p/WGt7YqjWBLxVdA 4XmC8RZIyk0GmD35dsmF88VQpVlBTGMdy6hIRIpYrUZmKMGCjJ+DNo6W8lMTxEAJh2b8 0BuddW60771twe9kcskt81EQl8UR6BlhQWaiaXpzypBmEc4391PfeXCdm4L/byZRr5MJ kqffGvNchihn2k/6BjmanhWQ2Sq3/85RnoMz2DXEnBmCzLkVyzoyppbWsdotB9VGJ/s4 YBmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Pw1LoX5aEGi8/1gaQ+fA9/sHVVZFYrW4J8ovX5aE9LA=; b=F0HllOuFZ1q9oJ/Ta3msvUEgsy/GbG6jeWwOsHNtf4k3GbiaDz+NwXwHW201C/6bj/ ee7vQlcDtcK3pfMJ/WMcF6jNwy1405MoKKvSXmE8TJin+4eniOoJCG1b2tQdW5mGA9AF UScZFKn4F+1l5QJRUxVDdU/zSYqKbPEVAT70aRcpd4HwZHStJDWaAmq7Thtp0R9Uzi/R p5uCd7Iufyoqos8E9hsU9we4Nk6cYAKyAi3kGVpnKjC1B66BqtbK9CB2qAaLh151IVf8 Zvstke5JKJCZZVxR/czMQCLqMCAehaJvvaOgfyIYppZ/ttuixXJ6b1r+iow/c8MVs8TG lo4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EXno+1ZO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n14si6980239edx.379.2021.06.21.09.38.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Jun 2021 09:38:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EXno+1ZO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvMwD-00085V-Fc for patch@linaro.org; Mon, 21 Jun 2021 12:38:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvMnH-0007EC-9j for qemu-devel@nongnu.org; Mon, 21 Jun 2021 12:29:03 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:42983) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lvMn9-0007Zy-46 for qemu-devel@nongnu.org; Mon, 21 Jun 2021 12:29:02 -0400 Received: by mail-wm1-x334.google.com with SMTP id l7-20020a05600c1d07b02901b0e2ebd6deso407081wms.1 for ; Mon, 21 Jun 2021 09:28:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Pw1LoX5aEGi8/1gaQ+fA9/sHVVZFYrW4J8ovX5aE9LA=; b=EXno+1ZOGeyQCHochh6AsuHlhmjzPBlfm9iBNtLx0uzVpLSSCVFYmHRcXy2x99NfVp kfhkMhVkpCMPtD06QndGiBkRLsQ49TeNtnyTFsWmngXw1Fn53v1OOqoY5ah7T016jAUS 7nHQAUpCIjr6YwWySPCfHnFEIyQA056F4Id3LaDkR/YB1KqAaIvGnLKDTpPInkwCoiU1 W8aEhfJwriHgqY0eSn+ROciffn1oiZizeZoY00bfKXIwccGzwvNqkszJs1st74KCJjLF rXcswrfpk4WoqojWkVAGKCvsvbFoS2QrWndN9xmNiLoIIQjz82Y41ostNIA2yekFOHYX 4D0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Pw1LoX5aEGi8/1gaQ+fA9/sHVVZFYrW4J8ovX5aE9LA=; b=OqjDMJ/9qxpgpmjA9rhNRfttlLQVr45E6f2lczk4XgWUDCn24rzcBqTl6F8L9kh/vy JX1quQfwbXed3YPaG2BPg9VhQTMxtMt1v4atsnoMp/YGUhcF1SLViDK9rjH/gTSAUwc8 c1PCnVhCqi3NCYi170BN3XcktlDtW1VEXDmWcUFCmHnLpV1xA6PcuSrFJjplVBp1YADe yWwrdyXr55cYamslbkbicavNeqyHadZQwRrBTkBdRS7o1YU2759FD8jDOdkA4/LvvIi0 tVEKuig3nfeRA0Axr7g73ursXb1tnJAHvH1v9sIRlMlAVKPS87HhXtY6Hm0yz4xYbWMj 0/QA== X-Gm-Message-State: AOAM531repkmFrgYjlf1SiTpk0hTS5iRZMDJs11wlVdNZT6ktT3Uv9Mh 8vz+yImybYFnGwqATCNoecpREyADeDVBeU5d X-Received: by 2002:a7b:c30f:: with SMTP id k15mr28572611wmj.128.1624292933076; Mon, 21 Jun 2021 09:28:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n65sm11615496wme.21.2021.06.21.09.28.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 09:28:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/57] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64 Date: Mon, 21 Jun 2021 17:27:56 +0100 Message-Id: <20210621162833.32535-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210621162833.32535-1-peter.maydell@linaro.org> References: <20210621162833.32535-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The Arm MVE VDUP implementation would like to be able to emit code to duplicate a byte or halfword value into an i32. We have code to do this already in tcg-op-gvec.c, so all we need to do is make the functions global. For consistency with other functions made available to the frontends: * we rename to tcg_gen_dup_* * we expose both the _i32 and _i64 forms * we provide the #define for a _tl form Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20210617121628.20116-10-peter.maydell@linaro.org --- include/tcg/tcg-op.h | 8 ++++++++ include/tcg/tcg.h | 1 - tcg/tcg-op-gvec.c | 20 ++++++++++---------- 3 files changed, 18 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index ef8a008ea74..1a2ae937583 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -338,6 +338,9 @@ void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); +/* Replicate a value of size @vece from @in to all the lanes in @out */ +void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); + static inline void tcg_gen_discard_i32(TCGv_i32 arg) { tcg_gen_op1_i32(INDEX_op_discard, arg); @@ -534,6 +537,9 @@ void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); +/* Replicate a value of size @vece from @in to all the lanes in @out */ +void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); + #if TCG_TARGET_REG_BITS == 64 static inline void tcg_gen_discard_i64(TCGv_i64 arg) { @@ -1127,6 +1133,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec +#define tcg_gen_dup_tl tcg_gen_dup_i64 #else #define tcg_gen_movi_tl tcg_gen_movi_i32 #define tcg_gen_mov_tl tcg_gen_mov_i32 @@ -1241,6 +1248,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec +#define tcg_gen_dup_tl tcg_gen_dup_i32 #endif #if UINTPTR_MAX == UINT32_MAX diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 064dab383bc..483e1e1f24e 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1331,7 +1331,6 @@ uint64_t dup_const(unsigned vece, uint64_t c); : (qemu_build_not_reached_always(), 0)) \ : dup_const(VECE, C)) - /* * Memory helpers that will be used by TCG generated code. */ diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 498a959839f..515db120cc6 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -386,7 +386,7 @@ uint64_t (dup_const)(unsigned vece, uint64_t c) } /* Duplicate IN into OUT as per VECE. */ -static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in) +void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in) { switch (vece) { case MO_8: @@ -404,7 +404,7 @@ static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in) } } -static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in) +void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in) { switch (vece) { case MO_8: @@ -578,15 +578,15 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, && (vece != MO_32 || !check_size_impl(oprsz, 4))) { t_64 = tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t_64, in_32); - gen_dup_i64(vece, t_64, t_64); + tcg_gen_dup_i64(vece, t_64, t_64); } else { t_32 = tcg_temp_new_i32(); - gen_dup_i32(vece, t_32, in_32); + tcg_gen_dup_i32(vece, t_32, in_32); } } else if (in_64) { /* We are given a 64-bit variable input. */ t_64 = tcg_temp_new_i64(); - gen_dup_i64(vece, t_64, in_64); + tcg_gen_dup_i64(vece, t_64, in_64); } else { /* We are given a constant input. */ /* For 64-bit hosts, use 64-bit constants for "simple" constants @@ -1311,14 +1311,14 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, } else if (g->fni8 && check_size_impl(oprsz, 8)) { TCGv_i64 t64 = tcg_temp_new_i64(); - gen_dup_i64(g->vece, t64, c); + tcg_gen_dup_i64(g->vece, t64, c); expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8); tcg_temp_free_i64(t64); } else if (g->fni4 && check_size_impl(oprsz, 4)) { TCGv_i32 t32 = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t32, c); - gen_dup_i32(g->vece, t32, t32); + tcg_gen_dup_i32(g->vece, t32, t32); expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4); tcg_temp_free_i32(t32); } else { @@ -2538,7 +2538,7 @@ void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) { TCGv_i64 tmp = tcg_temp_new_i64(); - gen_dup_i64(vece, tmp, c); + tcg_gen_dup_i64(vece, tmp, c); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); tcg_temp_free_i64(tmp); } @@ -2562,7 +2562,7 @@ void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) { TCGv_i64 tmp = tcg_temp_new_i64(); - gen_dup_i64(vece, tmp, c); + tcg_gen_dup_i64(vece, tmp, c); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors); tcg_temp_free_i64(tmp); } @@ -2586,7 +2586,7 @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) { TCGv_i64 tmp = tcg_temp_new_i64(); - gen_dup_i64(vece, tmp, c); + tcg_gen_dup_i64(vece, tmp, c); tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors); tcg_temp_free_i64(tmp); }