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[209.132.180.67]) by mx.google.com with ESMTP id gz5si12682125pbc.124.2015.03.29.22.24.58; Sun, 29 Mar 2015 22:25:00 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752256AbbC3FY6 (ORCPT + 5 others); Mon, 30 Mar 2015 01:24:58 -0400 Received: from mail-yh0-f50.google.com ([209.85.213.50]:35020 "EHLO mail-yh0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751953AbbC3FY5 (ORCPT ); Mon, 30 Mar 2015 01:24:57 -0400 Received: by yhfw71 with SMTP id w71so3319049yhf.2 for ; Sun, 29 Mar 2015 22:24:57 -0700 (PDT) X-Received: by 10.170.149.194 with SMTP id q185mr36314195ykc.90.1427693097299; Sun, 29 Mar 2015 22:24:57 -0700 (PDT) Received: from localhost.localdomain ([104.207.83.1]) by mx.google.com with ESMTPSA id g46sm9852584yhd.42.2015.03.29.22.24.53 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 29 Mar 2015 22:24:56 -0700 (PDT) From: Leo Yan To: Wei Xu , Dan Zhao , zhenwei.wang@hisilicon.com, Haojian Zhuang , Bintian Wang , mturquette@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: Leo Yan Subject: [PATCH v2 2/5] clk: hisi: add API for allocation clk data struct Date: Mon, 30 Mar 2015 13:24:21 +0800 Message-Id: <1427693064-11062-3-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427693064-11062-1-git-send-email-leo.yan@linaro.org> References: <1427693064-11062-1-git-send-email-leo.yan@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: leo.yan@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.192.53 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In the clk init function, it will read the register base address from dts and allocate the clk data structures. But for the some cases, the clock driver don't need init the reg's base address, which will directly access mmio region with syscon. So for clock's initialization, this patch adds one more API which is only for allocating clock data structure. Signed-off-by: Leo Yan --- drivers/clk/hisilicon/clk.c | 30 +++++++++++++++++++++++------- drivers/clk/hisilicon/clk.h | 2 ++ 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 1951b37..87f8173 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -38,16 +38,14 @@ static DEFINE_SPINLOCK(hisi_clk_lock); -struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, - int nr_clks) +struct hisi_clock_data __init *hisi_clk_alloc_data(struct device_node *np, + int nr_clks) { struct hisi_clock_data *clk_data; struct clk **clk_table; - void __iomem *base; - base = of_iomap(np, 0); - if (!base) { - pr_err("%s: failed to map clock registers\n", __func__); + if (!np) { + pr_err("%s: invalid device node handler\n", __func__); goto err; } @@ -56,7 +54,6 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, pr_err("%s: could not allocate clock data\n", __func__); goto err; } - clk_data->base = base; clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); if (!clk_table) { @@ -67,12 +64,31 @@ struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, clk_data->clk_data.clk_num = nr_clks; of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); return clk_data; + err_data: kfree(clk_data); err: return NULL; } +struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, + int nr_clks) +{ + struct hisi_clock_data *clk_data; + void __iomem *base; + + base = of_iomap(np, 0); + if (!base) { + pr_err("%s: failed to map clock registers\n", __func__); + return NULL; + } + + clk_data = hisi_clk_alloc_data(np, nr_clks); + if (clk_data) + clk_data->base = base; + return clk_data; +} + void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 31083ff..624f608 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -96,6 +96,8 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, u8, spinlock_t *); struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int); +struct hisi_clock_data __init *hisi_clk_alloc_data(struct device_node *np, + int nr_clks); void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, int, struct hisi_clock_data *); void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,