| Message ID | 20210709200339.17638-5-quic_vamslank@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Pdc, GCC and RPMh clock support for SDX65 | expand |
On Fri 09 Jul 15:03 CDT 2021, quic_vamslank@quicinc.com wrote: > From: Vamsi krishna Lanka <quic_vamslank@quicinc.com> > > Add support for clocks maintained by RPMh in SDX65 SoCs. > Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> > --- > drivers/clk/qcom/clk-rpmh.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > index 91dc390a583b..f3769b86e5d0 100644 > --- a/drivers/clk/qcom/clk-rpmh.c > +++ b/drivers/clk/qcom/clk-rpmh.c > @@ -477,6 +477,32 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { > .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), > }; > > +DEFINE_CLK_RPMH_ARC(sdx65, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4); > +DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); > +DEFINE_CLK_RPMH_VRM(sdx65, rf_clk4, rf_clk4_ao, "rfclka4", 1); > + > +static struct clk_hw *sdx65_rpmh_clocks[] = { > + [RPMH_CXO_CLK] = &sdx65_bi_tcxo.hw, > + [RPMH_CXO_CLK_A] = &sdx65_bi_tcxo_ao.hw, > + [RPMH_LN_BB_CLK1] = &sdx65_ln_bb_clk1.hw, > + [RPMH_LN_BB_CLK1_A] = &sdx65_ln_bb_clk1_ao.hw, > + [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, > + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, > + [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, > + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, > + [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, > + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, > + [RPMH_RF_CLK4] = &sdx65_rf_clk4.hw, > + [RPMH_RF_CLK4_A] = &sdx65_rf_clk4_ao.hw, > + [RPMH_IPA_CLK] = &sdm845_ipa.hw, > + [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, > +}; > + > +static const struct clk_rpmh_desc clk_rpmh_sdx65 = { > + .clks = sdx65_rpmh_clocks, > + .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), > +}; > + > DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); > DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); > DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); > @@ -618,6 +644,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { > { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, > { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, > { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, > + { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, > { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, > { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, > { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, > -- > 2.32.0 >
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 91dc390a583b..f3769b86e5d0 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -477,6 +477,32 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), }; +DEFINE_CLK_RPMH_ARC(sdx65, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4); +DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); +DEFINE_CLK_RPMH_VRM(sdx65, rf_clk4, rf_clk4_ao, "rfclka4", 1); + +static struct clk_hw *sdx65_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &sdx65_bi_tcxo.hw, + [RPMH_CXO_CLK_A] = &sdx65_bi_tcxo_ao.hw, + [RPMH_LN_BB_CLK1] = &sdx65_ln_bb_clk1.hw, + [RPMH_LN_BB_CLK1_A] = &sdx65_ln_bb_clk1_ao.hw, + [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, + [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, + [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw, + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw, + [RPMH_RF_CLK4] = &sdx65_rf_clk4.hw, + [RPMH_RF_CLK4_A] = &sdx65_rf_clk4_ao.hw, + [RPMH_IPA_CLK] = &sdm845_ipa.hw, + [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sdx65 = { + .clks = sdx65_rpmh_clocks, + .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), +}; + DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); @@ -618,6 +644,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, + { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},