@@ -20,6 +20,13 @@ config SND_SOC_LPASS_IPQ806X
select SND_SOC_LPASS_CPU
select SND_SOC_LPASS_PLATFORM
+config SND_SOC_LPASS_APQ8016
+ tristate
+ depends on SND_SOC_QCOM
+ select SND_SOC_LPASS_CPU
+ select SND_SOC_LPASS_PLATFORM
+
+
config SND_SOC_STORM
tristate "ASoC I2S support for Storm boards"
depends on (ARCH_QCOM && SND_SOC_QCOM) || COMPILE_TEST
@@ -2,10 +2,12 @@
snd-soc-lpass-cpu-objs := lpass-cpu.o
snd-soc-lpass-platform-objs := lpass-platform.o
snd-soc-lpass-ipq806x-objs := lpass-ipq806x.o
+snd-soc-lpass-apq8016-objs := lpass-apq8016.o
obj-$(CONFIG_SND_SOC_LPASS_CPU) += snd-soc-lpass-cpu.o
obj-$(CONFIG_SND_SOC_LPASS_PLATFORM) += snd-soc-lpass-platform.o
obj-$(CONFIG_SND_SOC_LPASS_IPQ806X) += snd-soc-lpass-ipq806x.o
+obj-$(CONFIG_SND_SOC_LPASS_APQ8016) += snd-soc-lpass-apq8016.o
# Machine
snd-soc-storm-objs := storm.o
new file mode 100644
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * lpass-apq8016.c -- ALSA SoC CPU DAI driver for APQ8016 LPASS
+ *
+ */
+
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dai.h>
+
+#include <dt-bindings/sound/apq8016-lpass.h>
+#include "lpass-lpaif-reg.h"
+#include "lpass.h"
+
+static struct snd_soc_dai_driver apq8016_lpass_cpu_dai_driver[] = {
+ [MI2S_PRIMARY] = {
+ .id = MI2S_PRIMARY,
+ .name = "Primary MI2S",
+ .playback = {
+ .stream_name = "Primary Playback",
+ .formats = SNDRV_PCM_FMTBIT_S16 |
+ SNDRV_PCM_FMTBIT_S24 |
+ SNDRV_PCM_FMTBIT_S32,
+ .rates = SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_32000 |
+ SNDRV_PCM_RATE_48000 |
+ SNDRV_PCM_RATE_96000,
+ .rate_min = 8000,
+ .rate_max = 96000,
+ .channels_min = 1,
+ .channels_max = 8,
+ },
+ .probe = &lpass_cpu_dai_probe,
+ .ops = &lpass_cpu_dai_ops,
+ },
+ [MI2S_SECONDARY] = {
+ .id = MI2S_SECONDARY,
+ .name = "Secondary MI2S",
+ .playback = {
+ .stream_name = "Secondary Playback",
+ .formats = SNDRV_PCM_FMTBIT_S16 |
+ SNDRV_PCM_FMTBIT_S24 |
+ SNDRV_PCM_FMTBIT_S32,
+ .rates = SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_32000 |
+ SNDRV_PCM_RATE_48000 |
+ SNDRV_PCM_RATE_96000,
+ .rate_min = 8000,
+ .rate_max = 96000,
+ .channels_min = 1,
+ .channels_max = 8,
+ },
+ .probe = &lpass_cpu_dai_probe,
+ .ops = &lpass_cpu_dai_ops,
+ },
+ [MI2S_TERTIARY] = {
+ .id = MI2S_TERTIARY,
+ .name = "Tertiary MI2S",
+ .capture = {
+ .stream_name = "Tertiary Capture",
+ .formats = SNDRV_PCM_FMTBIT_S16 |
+ SNDRV_PCM_FMTBIT_S24 |
+ SNDRV_PCM_FMTBIT_S32,
+ .rates = SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_32000 |
+ SNDRV_PCM_RATE_48000 |
+ SNDRV_PCM_RATE_96000,
+ .rate_min = 8000,
+ .rate_max = 96000,
+ .channels_min = 1,
+ .channels_max = 8,
+ },
+ .probe = &lpass_cpu_dai_probe,
+ .ops = &lpass_cpu_dai_ops,
+ },
+ [MI2S_QUATERNARY] = {
+ .id = MI2S_QUATERNARY,
+ .name = "Quatenary MI2S",
+ .playback = {
+ .stream_name = "Quatenary Playback",
+ .formats = SNDRV_PCM_FMTBIT_S16 |
+ SNDRV_PCM_FMTBIT_S24 |
+ SNDRV_PCM_FMTBIT_S32,
+ .rates = SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_32000 |
+ SNDRV_PCM_RATE_48000 |
+ SNDRV_PCM_RATE_96000,
+ .rate_min = 8000,
+ .rate_max = 96000,
+ .channels_min = 1,
+ .channels_max = 8,
+ },
+ .capture = {
+ .stream_name = "Quatenary Capture",
+ .formats = SNDRV_PCM_FMTBIT_S16 |
+ SNDRV_PCM_FMTBIT_S24 |
+ SNDRV_PCM_FMTBIT_S32,
+ .rates = SNDRV_PCM_RATE_8000 |
+ SNDRV_PCM_RATE_16000 |
+ SNDRV_PCM_RATE_32000 |
+ SNDRV_PCM_RATE_48000 |
+ SNDRV_PCM_RATE_96000,
+ .rate_min = 8000,
+ .rate_max = 96000,
+ .channels_min = 1,
+ .channels_max = 8,
+ },
+ .probe = &lpass_cpu_dai_probe,
+ .ops = &lpass_cpu_dai_ops,
+ },
+};
+
+static int apq8016_lpass_alloc_dma_channel(struct lpass_data *drvdata)
+{
+ struct lpass_variant *v = drvdata->variant;
+ int chan = find_first_zero_bit(&drvdata->rdma_ch_bit_map,
+ v->rdma_channels);
+
+ if (chan >= v->rdma_channels)
+ return -EBUSY;
+
+ set_bit(chan, &drvdata->rdma_ch_bit_map);
+
+ return chan;
+}
+
+static int apq8016_lpass_free_dma_channel(struct lpass_data *drvdata, int chan)
+{
+ clear_bit(chan, &drvdata->rdma_ch_bit_map);
+
+ return 0;
+}
+
+static int apq8016_lpass_init(struct platform_device *pdev)
+{
+ struct lpass_data *drvdata = platform_get_drvdata(pdev);
+ struct device_node *np = pdev->dev.of_node;
+ int ret;
+
+ drvdata->pcnoc_mport_clk = of_clk_get_by_name(np, "pcnoc-mport-clk");
+ if (IS_ERR(drvdata->pcnoc_mport_clk)) {
+ dev_err(&pdev->dev, "%s() error getting pcnoc-mport-clk: %ld\n",
+ __func__, PTR_ERR(drvdata->pcnoc_mport_clk));
+ return PTR_ERR(drvdata->pcnoc_mport_clk);
+ }
+
+ ret = clk_prepare_enable(drvdata->pcnoc_mport_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "%s() Error enabling ahbix_clk: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ drvdata->pcnoc_sway_clk = of_clk_get_by_name(np, "pcnoc-sway-clk");
+ if (IS_ERR(drvdata->pcnoc_sway_clk)) {
+ dev_err(&pdev->dev, "%s() error getting pcnoc-sway-clk: %ld\n",
+ __func__, PTR_ERR(drvdata->pcnoc_sway_clk));
+ return PTR_ERR(drvdata->pcnoc_sway_clk);
+ }
+
+ ret = clk_prepare_enable(drvdata->pcnoc_sway_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "%s() Error enabling ahbix_clk: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int apq8016_lpass_exit(struct platform_device *pdev)
+{
+ struct lpass_data *drvdata = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(drvdata->pcnoc_mport_clk);
+ clk_disable_unprepare(drvdata->pcnoc_sway_clk);
+
+ return 0;
+}
+
+
+struct lpass_variant apq8016_data = {
+ .i2sctrl_reg_base = 0x1000,
+ .i2sctrl_reg_stride = 0x1000,
+ .i2s_ports = 4,
+ .irq_reg_base = 0x6000,
+ .irq_reg_stride = 0x1000,
+ .irq_ports = 3,
+ .rdma_reg_base = 0x8400,
+ .rdma_reg_stride = 0x1000,
+ .rdma_channels = 2,
+ .rdmactl_audif_start = 1,
+ .no_osr_clk = true,
+ .dai_driver = apq8016_lpass_cpu_dai_driver,
+ .num_dai = ARRAY_SIZE(apq8016_lpass_cpu_dai_driver),
+ .init = apq8016_lpass_init,
+ .exit = apq8016_lpass_exit,
+ .alloc_dma_channel = apq8016_lpass_alloc_dma_channel,
+ .free_dma_channel = apq8016_lpass_free_dma_channel,
+};
+
+static const struct of_device_id apq8016_lpass_cpu_device_id[] = {
+ { .compatible = "qcom,lpass-cpu-apq8016", .data = &apq8016_data },
+ {}
+};
+MODULE_DEVICE_TABLE(of, apq8016_lpass_cpu_device_id);
+
+static struct platform_driver lpass_cpu_platform_driver = {
+ .driver = {
+ .name = "apq8016-lpass-cpu",
+ .of_match_table = of_match_ptr(apq8016_lpass_cpu_device_id),
+ },
+ .probe = lpass_cpu_platform_probe,
+ .remove = lpass_cpu_platform_remove,
+};
+module_platform_driver(lpass_cpu_platform_driver);
+
+MODULE_DESCRIPTION("APQ8016 LPASS CPU Driver");
+MODULE_LICENSE("GPL v2");
+
@@ -54,6 +54,10 @@ struct lpass_data {
/* used it for handling interrupt per dma channel */
struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
+
+ /* 8016 specific */
+ struct clk *pcnoc_mport_clk;
+ struct clk *pcnoc_sway_clk;
};
/* Vairant data per each SOC */
This patch adds apq8016 lpass driver support. APQ8016 has 4 MI2S which can be routed to one internal codec and 2 external codec interfaces. Primary, Secondary, Quaternary I2S can do Rx(playback) and Tertiary and Quaternary can do Tx(capture). Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> --- sound/soc/qcom/Kconfig | 7 ++ sound/soc/qcom/Makefile | 2 + sound/soc/qcom/lpass-apq8016.c | 243 +++++++++++++++++++++++++++++++++++++++++ sound/soc/qcom/lpass.h | 4 + 4 files changed, 256 insertions(+) create mode 100644 sound/soc/qcom/lpass-apq8016.c