diff mbox

[1/3] clk: qcom: Add MSM8916 iommu clocks

Message ID 1431428438-8171-1-git-send-email-georgi.djakov@linaro.org
State New
Headers show

Commit Message

Georgi Djakov May 12, 2015, 11 a.m. UTC 
Add support for the msm8916 TCU clocks that are needed for IOMMU.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8916.c               |   78 ++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8916.h |    4 ++
 2 files changed, 82 insertions(+)

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Comments

Georgi Djakov May 13, 2015, 4:45 p.m. UTC | #1 
On 05/13/2015 10:36 AM, Stephen Boyd wrote:
> On 05/12, Georgi Djakov wrote:
>> Add support for the msm8916 TCU clocks that are needed for IOMMU.
>>
>> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
>> ---
> 
> Applied to clk-next
> 

Hi Stephen,
Just got a report that this patch has some issues - gcc_bimc_clk
may get disabled by the CCF, which turns out to be not good.
So I am going to remove it from the chain leaving only the
bimc_ddr_clk_src as the parent of apss_tcu and gfx_tcu clocks.
Will re-send this series soon. Apologies for the extra work.

Thanks,
Georgi
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diff mbox

Patch

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index c66f7bc2ae87..7ad4c3751f43 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -2358,6 +2358,80 @@  static struct clk_branch gcc_sdcc2_apps_clk = {
 	},
 };
 
+static const struct freq_tbl ftbl_bimc_ddr_clk[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(100000000, P_GPLL0, 8, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
+	F(266500000, P_BIMC, 4, 0, 0),
+	F(400000000, P_GPLL0, 2, 0, 0),
+	F(533000000, P_BIMC, 2, 0, 0),
+	F(800000000, P_GPLL0, 1, 0, 0),
+	F(1066000000, P_BIMC, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 bimc_ddr_clk_src = {
+	.cmd_rcgr = 0x32004,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_bimc_map,
+	.freq_tbl = ftbl_bimc_ddr_clk,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "bimc_ddr_clk_src",
+		.parent_names = gcc_xo_gpll0_bimc,
+		.num_parents = 3,
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_bimc_clk = {
+	.halt_reg = 0x3101c,
+	.clkr = {
+		.enable_reg = 0x3101c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_bimc_clk",
+			.parent_names = (const char *[]){
+					"bimc_ddr_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_apss_tcu_clk = {
+	.halt_reg = 0x12018,
+	.clkr = {
+		.enable_reg = 0x4500c,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_apss_tcu_clk",
+			.parent_names = (const char *[]){
+				"gcc_bimc_clk",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_gfx_tcu_clk = {
+	.halt_reg = 0x12020,
+	.clkr = {
+		.enable_reg = 0x4500c,
+		.enable_mask = BIT(2),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_gfx_tcu_clk",
+			.parent_names = (const char *[]){
+				"gcc_bimc_clk",
+			},
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_gtcu_ahb_clk = {
 	.halt_reg = 0x12044,
 	.clkr = {
@@ -2701,6 +2775,10 @@  static struct clk_regmap *gcc_msm8916_clocks[] = {
 	[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
 	[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
 	[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
+	[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
+	[GCC_BIMC_CLK] = &gcc_bimc_clk.clkr,
+	[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
+	[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_msm8916_resets[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
index e430f644dd6c..0af3b49431df 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -152,5 +152,9 @@ 
 #define GCC_VENUS0_AHB_CLK			135
 #define GCC_VENUS0_AXI_CLK			136
 #define GCC_VENUS0_VCODEC0_CLK			137
+#define BIMC_DDR_CLK_SRC			138
+#define GCC_BIMC_CLK				139
+#define GCC_APSS_TCU_CLK			140
+#define GCC_GFX_TCU_CLK				141
 
 #endif