| Message ID | 1626762588-6020-2-git-send-email-yongqiang.niu@mediatek.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v5] drm/mediatek: add dither 6 setting | expand |
Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年7月20日 週二 下午2:30寫道： > > dither 6 setting is missed in a6b7c98afdca > bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable > bit 2 is rdither_en(Enables running order dithering), need disable > > Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common()) > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 99cbf44..7dd8e05 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -26,6 +26,7 @@ > #define DISP_OD_CFG 0x0020 > #define DISP_OD_SIZE 0x0030 > #define DISP_DITHER_5 0x0114 > +#define DISP_DITHER_6 0x0118 > #define DISP_DITHER_7 0x011c > #define DISP_DITHER_15 0x013c > #define DISP_DITHER_16 0x0140 > @@ -135,6 +136,7 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, > > if (bpc >= MTK_MIN_BPC) { > mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5); > + mtk_ddp_write(cmdq_pkt, 0x3002, cmdq_reg, regs, DISP_DITHER_6); Symbolized 0x3002. BIT(1) is lfsr_en. Regards, Chun-Kuang. > mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7); > mtk_ddp_write(cmdq_pkt, > DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > -- > 1.8.1.1.dirty >
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 99cbf44..7dd8e05 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -26,6 +26,7 @@ #define DISP_OD_CFG 0x0020 #define DISP_OD_SIZE 0x0030 #define DISP_DITHER_5 0x0114 +#define DISP_DITHER_6 0x0118 #define DISP_DITHER_7 0x011c #define DISP_DITHER_15 0x013c #define DISP_DITHER_16 0x0140 @@ -135,6 +136,7 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, if (bpc >= MTK_MIN_BPC) { mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5); + mtk_ddp_write(cmdq_pkt, 0x3002, cmdq_reg, regs, DISP_DITHER_6); mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
dither 6 setting is missed in a6b7c98afdca bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable bit 2 is rdither_en(Enables running order dithering), need disable Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common()) Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ 1 file changed, 2 insertions(+)