diff mbox series

[v4,3/3] arm64: dts: renesas: r9a07g044: Add CANFD node

Message ID 20210727133022.634-4-prabhakar.mahadev-lad.rj@bp.renesas.com
State New
Headers show
Series Renesas RZ/G2L CANFD support | expand

Commit Message

Prabhakar Mahadev Lad July 27, 2021, 1:30 p.m. UTC 
Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)

Comments

Marc Kleine-Budde Aug. 4, 2021, 7:58 a.m. UTC | #1 
On 27.07.2021 14:30:22, Lad Prabhakar wrote:
> Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> index 9a7489dc70d1..51655c09f1f8 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -13,6 +13,13 @@
>  	#address-cells = <2>;
>  	#size-cells = <2>;
>  
> +	/* External CAN clock - to be overridden by boards that provide it */
> +	can_clk: can {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <0>;
> +	};
> +
>  	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
>  	extal_clk: extal {
>  		compatible = "fixed-clock";
> @@ -89,6 +96,40 @@
>  			status = "disabled";
>  		};
>  
> +		canfd: can@10050000 {
> +			compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
> +			reg = <0 0x10050000 0 0x8000>;
> +			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "g_err", "g_recc",
> +					  "ch0_err", "ch0_rec", "ch0_trx",
> +					  "ch1_err", "ch1_rec", "ch1_trx";
> +			clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
> +				 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
> +				 <&can_clk>;
> +			clock-names = "fck", "canfd", "can_clk";
> +			assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
> +			assigned-clock-rates = <50000000>;
> +			resets = <&cpg R9A07G044_CANFD_RSTP_N>,
> +				 <&cpg R9A07G044_CANFD_RSTC_N>;
> +			reset-names = "rstp_n", "rstc_n";
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +
> +			channel0 {
> +				status = "disabled";
> +			};
> +			channel1 {
> +				status = "disabled";
> +			};
> +		};
> +
>  		i2c0: i2c@10058000 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;

This doesn't apply to net-next/master, the r9a07g044.dtsi doesn't have a
i2c0 node at all. There isn't a i2c0 node in Linus' master branch, yet.

Marc
Prabhakar Aug. 4, 2021, 8:11 a.m. UTC | #2 
Hi Marc,

On Wed, Aug 4, 2021 at 8:59 AM Marc Kleine-Budde <mkl@pengutronix.de> wrote:
>
> On 27.07.2021 14:30:22, Lad Prabhakar wrote:
> > Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
> >  1 file changed, 41 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > index 9a7489dc70d1..51655c09f1f8 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > @@ -13,6 +13,13 @@
> >       #address-cells = <2>;
> >       #size-cells = <2>;
> >
> > +     /* External CAN clock - to be overridden by boards that provide it */
> > +     can_clk: can {
> > +             compatible = "fixed-clock";
> > +             #clock-cells = <0>;
> > +             clock-frequency = <0>;
> > +     };
> > +
> >       /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> >       extal_clk: extal {
> >               compatible = "fixed-clock";
> > @@ -89,6 +96,40 @@
> >                       status = "disabled";
> >               };
> >
> > +             canfd: can@10050000 {
> > +                     compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
> > +                     reg = <0 0x10050000 0 0x8000>;
> > +                     interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
> > +                     interrupt-names = "g_err", "g_recc",
> > +                                       "ch0_err", "ch0_rec", "ch0_trx",
> > +                                       "ch1_err", "ch1_rec", "ch1_trx";
> > +                     clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
> > +                              <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
> > +                              <&can_clk>;
> > +                     clock-names = "fck", "canfd", "can_clk";
> > +                     assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
> > +                     assigned-clock-rates = <50000000>;
> > +                     resets = <&cpg R9A07G044_CANFD_RSTP_N>,
> > +                              <&cpg R9A07G044_CANFD_RSTC_N>;
> > +                     reset-names = "rstp_n", "rstc_n";
> > +                     power-domains = <&cpg>;
> > +                     status = "disabled";
> > +
> > +                     channel0 {
> > +                             status = "disabled";
> > +                     };
> > +                     channel1 {
> > +                             status = "disabled";
> > +                     };
> > +             };
> > +
> >               i2c0: i2c@10058000 {
> >                       #address-cells = <1>;
> >                       #size-cells = <0>;
>
> This doesn't apply to net-next/master, the r9a07g044.dtsi doesn't have a
> i2c0 node at all. There isn't a i2c0 node in Linus' master branch, yet.
>
I had based the patch on top [1] (sorry I should have mentioned the
dependency), usually Geert picks up the DTS/I patches and queues it
via ARM tree. Shall I rebase it on net-next and re-send ?

@Geert Uytterhoeven Is that OK ?

[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/log/?h=renesas-arm-dt-for-v5.15

Cheers,
Prabhakar

> Marc
>
> --
> Pengutronix e.K.                 | Marc Kleine-Budde           |
> Embedded Linux                   | https://www.pengutronix.de  |
> Vertretung West/Dortmund         | Phone: +49-231-2826-924     |
> Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-5555 |
Geert Uytterhoeven Aug. 9, 2021, 1:05 p.m. UTC | #3 
Hi Marc,

On Wed, Aug 4, 2021 at 10:11 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Wed, Aug 4, 2021 at 8:59 AM Marc Kleine-Budde <mkl@pengutronix.de> wrote:
> > On 27.07.2021 14:30:22, Lad Prabhakar wrote:
> > > Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > ---
> > >  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 41 ++++++++++++++++++++++
> > >  1 file changed, 41 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > index 9a7489dc70d1..51655c09f1f8 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> > > @@ -13,6 +13,13 @@
> > >       #address-cells = <2>;
> > >       #size-cells = <2>;
> > >
> > > +     /* External CAN clock - to be overridden by boards that provide it */
> > > +     can_clk: can {
> > > +             compatible = "fixed-clock";
> > > +             #clock-cells = <0>;
> > > +             clock-frequency = <0>;
> > > +     };
> > > +
> > >       /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > >       extal_clk: extal {
> > >               compatible = "fixed-clock";
> > > @@ -89,6 +96,40 @@
> > >                       status = "disabled";
> > >               };
> > >
> > > +             canfd: can@10050000 {
> > > +                     compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
> > > +                     reg = <0 0x10050000 0 0x8000>;
> > > +                     interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
> > > +                     interrupt-names = "g_err", "g_recc",
> > > +                                       "ch0_err", "ch0_rec", "ch0_trx",
> > > +                                       "ch1_err", "ch1_rec", "ch1_trx";
> > > +                     clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
> > > +                              <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
> > > +                              <&can_clk>;
> > > +                     clock-names = "fck", "canfd", "can_clk";
> > > +                     assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
> > > +                     assigned-clock-rates = <50000000>;
> > > +                     resets = <&cpg R9A07G044_CANFD_RSTP_N>,
> > > +                              <&cpg R9A07G044_CANFD_RSTC_N>;
> > > +                     reset-names = "rstp_n", "rstc_n";
> > > +                     power-domains = <&cpg>;
> > > +                     status = "disabled";
> > > +
> > > +                     channel0 {
> > > +                             status = "disabled";
> > > +                     };
> > > +                     channel1 {
> > > +                             status = "disabled";
> > > +                     };
> > > +             };
> > > +
> > >               i2c0: i2c@10058000 {
> > >                       #address-cells = <1>;
> > >                       #size-cells = <0>;
> >
> > This doesn't apply to net-next/master, the r9a07g044.dtsi doesn't have a
> > i2c0 node at all. There isn't a i2c0 node in Linus' master branch, yet.
> >
> I had based the patch on top [1] (sorry I should have mentioned the
> dependency), usually Geert picks up the DTS/I patches and queues it
> via ARM tree. Shall I rebase it on net-next and re-send ?
>
> @Geert Uytterhoeven Is that OK ?

Please do not take Renesas DTS patches through the netdev tree
(or any other subsystem tree).

> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/log/?h=renesas-arm-dt-for-v5.15


Gr{oetje,eeting}s,

                        Geert
Marc Kleine-Budde Aug. 9, 2021, 1:22 p.m. UTC | #4 
On 09.08.2021 15:05:30, Geert Uytterhoeven wrote:
> > > This doesn't apply to net-next/master, the r9a07g044.dtsi doesn't have a
> > > i2c0 node at all. There isn't a i2c0 node in Linus' master branch, yet.
> > >
> > I had based the patch on top [1] (sorry I should have mentioned the
> > dependency), usually Geert picks up the DTS/I patches and queues it
> > via ARM tree. Shall I rebase it on net-next and re-send ?
> >
> > @Geert Uytterhoeven Is that OK ?
> 
> Please do not take Renesas DTS patches through the netdev tree
> (or any other subsystem tree).

Ok, I'm taking path 1 and 2 then.

regards,
Marc
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 9a7489dc70d1..51655c09f1f8 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -13,6 +13,13 @@ 
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	/* External CAN clock - to be overridden by boards that provide it */
+	can_clk: can {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
 	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
 	extal_clk: extal {
 		compatible = "fixed-clock";
@@ -89,6 +96,40 @@ 
 			status = "disabled";
 		};
 
+		canfd: can@10050000 {
+			compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
+			reg = <0 0x10050000 0 0x8000>;
+			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "g_err", "g_recc",
+					  "ch0_err", "ch0_rec", "ch0_trx",
+					  "ch1_err", "ch1_rec", "ch1_trx";
+			clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
+				 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
+				 <&can_clk>;
+			clock-names = "fck", "canfd", "can_clk";
+			assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
+			assigned-clock-rates = <50000000>;
+			resets = <&cpg R9A07G044_CANFD_RSTP_N>,
+				 <&cpg R9A07G044_CANFD_RSTC_N>;
+			reset-names = "rstp_n", "rstc_n";
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			channel0 {
+				status = "disabled";
+			};
+			channel1 {
+				status = "disabled";
+			};
+		};
+
 		i2c0: i2c@10058000 {
 			#address-cells = <1>;
 			#size-cells = <0>;