[6/9] arm64: dts: rockchip: add missing rk3568 cru phandles

Message ID 20210728135534.703028-7-pgwipeout@gmail.com
State New
Headers show
Series
  • fixes and enablement for rk356x
Related show

Commit Message

Peter Geis July 28, 2021, 1:55 p.m.
The grf and pmugrf phandles are necessary for the pmucru and cru to
modify clocks. Add these phandles to permit adjusting the clock rates
and muxes.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
 1 file changed, 3 insertions(+)

Comments

Peter Geis July 28, 2021, 2:18 p.m. | #1
On Wed, Jul 28, 2021 at 10:06 AM Heiko Stübner <heiko@sntech.de> wrote:
>
> Hi Peter,
>
> Am Mittwoch, 28. Juli 2021, 15:55:31 CEST schrieb Peter Geis:
> > The grf and pmugrf phandles are necessary for the pmucru and cru to
> > modify clocks. Add these phandles to permit adjusting the clock rates
> > and muxes.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index 0905fac0726a..8ba0516eedd8 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -218,6 +218,8 @@ grf: syscon@fdc60000 {
> >       pmucru: clock-controller@fdd00000 {
> >               compatible = "rockchip,rk3568-pmucru";
> >               reg = <0x0 0xfdd00000 0x0 0x1000>;
> > +             rockchip,grf = <&grf>;
> > +             rockchip,pmugrf = <&pmugrf>;
>
> I don't think the pmucru needs both and in fact the mainline
> clock driver should just reference its specific grf at all, i.e.
>         pmucru -> pmugrf (via the rockchip,grf handle)
>         cru -> grf
>
> I've not seen anything breaking this scope so far.

I thought the same thing as well, but for some reason the driver
refuses to apply assigned-clocks to the plls unless these are all
present.
If the driver can get these assignments automatically eventually,
perhaps it's a loading order issue?

Thinking about it, it's probably the grf and pmugrf haven't probed
when the driver is attempting to assign these, and tying them together
forces the probe to happen first.

>
>
> Heiko
>
> >               #clock-cells = <1>;
> >               #reset-cells = <1>;
> >       };
> > @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 {
> >       cru: clock-controller@fdd20000 {
> >               compatible = "rockchip,rk3568-cru";
> >               reg = <0x0 0xfdd20000 0x0 0x1000>;
> > +             rockchip,grf = <&grf>;
> >               #clock-cells = <1>;
> >               #reset-cells = <1>;
> >       };
> >
>
>
>
>

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 0905fac0726a..8ba0516eedd8 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -218,6 +218,8 @@  grf: syscon@fdc60000 {
 	pmucru: clock-controller@fdd00000 {
 		compatible = "rockchip,rk3568-pmucru";
 		reg = <0x0 0xfdd00000 0x0 0x1000>;
+		rockchip,grf = <&grf>;
+		rockchip,pmugrf = <&pmugrf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -225,6 +227,7 @@  pmucru: clock-controller@fdd00000 {
 	cru: clock-controller@fdd20000 {
 		compatible = "rockchip,rk3568-cru";
 		reg = <0x0 0xfdd20000 0x0 0x1000>;
+		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};