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[2603:800c:3202:ffa7:dcaa:9e71:a2b2:2604]) by smtp.gmail.com with ESMTPSA id gg3sm947137pjb.35.2021.07.28.17.50.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 17:50:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.2 41/43] tcg: Add helper_unaligned_mmu for user-only sigbus Date: Wed, 28 Jul 2021 14:46:45 -1000 Message-Id: <20210729004647.282017-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210729004647.282017-1-richard.henderson@linaro.org> References: <20210729004647.282017-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" To be called from tcg generated code on hosts that support unaligned accesses natively, in response to an access that is supposed to be aligned. Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 5 +++++ accel/tcg/user-exec.c | 13 ++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 8c86365611..a934bed042 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); +#else + +void QEMU_NORETURN helper_unaligned_mmu(CPUArchState *env, target_ulong addr, + uint32_t type, uintptr_t ra); + #endif /* CONFIG_SOFTMMU */ #endif /* TCG_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index e8a82dd43f..5cbae7a7cc 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/atomic128.h" #include "trace/trace-root.h" +#include "tcg/tcg-ldst.h" #undef EAX #undef ECX @@ -866,9 +867,9 @@ static void validate_memop(MemOpIdx oi, MemOp expected) #endif } -static void cpu_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t ra) +static void QEMU_NORETURN +cpu_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, + int mmu_idx, uintptr_t ra) { CPUClass *cc = CPU_GET_CLASS(cpu); @@ -876,6 +877,12 @@ static void cpu_unaligned_access(CPUState *cpu, vaddr addr, g_assert_not_reached(); } +void helper_unaligned_mmu(CPUArchState *env, target_ulong addr, + uint32_t access_type, uintptr_t ra) +{ + cpu_unaligned_access(env_cpu(env), addr, access_type, MMU_USER_IDX, ra); +} + static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type) {