| Message ID | 1627581885-32165-4-git-send-email-sibis@codeaurora.org |
|---|---|
| State | Accepted |
| Commit | 11e03d692101e484df9322f892a8b6e111a82bfd |
| Headers | show |
| Series | [1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 | expand |
Quoting Sibi Sankar (2021-07-29 11:04:44) > Fixup the register regions used by the cpufreq node on SC7280 SoC to > support per core L3 DCVS. > > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
On 2021-08-31 22:34, Bjorn Andersson wrote: > On Tue 31 Aug 08:30 PDT 2021, Matthias Kaehlcke wrote: > >> On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote: >> > Fixup the register regions used by the cpufreq node on SC7280 SoC to >> > support per core L3 DCVS. >> > >> > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") >> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> >> >> This patch landed in the Bjorn's tree, however the corresponding >> driver >> change ("cpufreq: qcom: Re-arrange register offsets to support per >> core >> L3 DCVS" / >> https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@codeaurora.org/) >> did not land in any maintainer tree yet AFAIK. IIUC the DT change >> alone >> breaks cpufreq since the changed register regions require the changed >> offset in the cpufreq driver. >> > > Thanks for the note Matthias, it must have slipped by as I scraped the > inbox for things that looked ready. > > I'm actually not in favor of splitting these memory blocks in DT to > facilitate the Linux implementation of splitting that in multiple > drivers... > > But I've not been following up on that discussion. > > Regards, > Bjorn > >> Sibi, please confirm or clarify that my concern is unwarranted. Let's drop the patch asap as it breaks SC7280 cpufreq on lnext without the driver changes.
Hi, On Sun, Sep 5, 2021 at 8:20 PM Sibi Sankar <sibis@codeaurora.org> wrote: > > On 2021-08-31 22:34, Bjorn Andersson wrote: > > On Tue 31 Aug 08:30 PDT 2021, Matthias Kaehlcke wrote: > > > >> On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote: > >> > Fixup the register regions used by the cpufreq node on SC7280 SoC to > >> > support per core L3 DCVS. > >> > > >> > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") > >> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > >> > >> This patch landed in the Bjorn's tree, however the corresponding > >> driver > >> change ("cpufreq: qcom: Re-arrange register offsets to support per > >> core > >> L3 DCVS" / > >> https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@codeaurora.org/) > >> did not land in any maintainer tree yet AFAIK. IIUC the DT change > >> alone > >> breaks cpufreq since the changed register regions require the changed > >> offset in the cpufreq driver. > >> > > > > Thanks for the note Matthias, it must have slipped by as I scraped the > > inbox for things that looked ready. > > > > I'm actually not in favor of splitting these memory blocks in DT to > > facilitate the Linux implementation of splitting that in multiple > > drivers... > > > > But I've not been following up on that discussion. > > > > Regards, > > Bjorn > > > >> Sibi, please confirm or clarify that my concern is unwarranted. > > Let's drop the patch asap as it breaks > SC7280 cpufreq on lnext without the driver > changes. It's already landed so we need a revert: https://lore.kernel.org/r/20210907121220.1.I08460f490473b70de0d768db45f030a4d5c17828@changeid/ -Doug
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5764c5b5cae1..ddb8697aff9f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1829,9 +1829,9 @@ cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; - reg = <0 0x18591000 0 0x1000>, - <0 0x18592000 0 0x1000>, - <0 0x18593000 0 0x1000>; + reg = <0 0x18591100 0 0x900>, + <0 0x18592100 0 0x900>, + <0 0x18593100 0 0x900>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>;
Fixup the register regions used by the cpufreq node on SC7280 SoC to support per core L3 DCVS. Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") Signed-off-by: Sibi Sankar <sibis@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)