diff mbox

arm64 softfloat

Message ID 20150602145531.GK8790@bivouac.eciton.net
State Accepted
Commit 43d4231432838821cabe4f6aea4f0f50e87af9c4
Headers show

Commit Message

Leif Lindholm June 2, 2015, 2:55 p.m. UTC 
On Tue, Jun 02, 2015 at 02:25:15PM +0200, Vladimir 'phcoder' Serbinenko wrote:
> Please give more details as to where we have floats. We shouldn't have any

Ok, seems I was tripping over myself with the internal compiler error
workaround (-mgeneral-regs-only), and applying it on the host tools
as well, where +nofp was (correctly) not being enforced, causing a
clash.

So, rewinding a bit - in order to work around the gcc 5.1 build issue
(which is not Fedora specific), we can use -mgeneral-regs-only
instead of -march=armv8-a+nofp. If we do this, we can also get
rid of the arm64-specific twiddling that drops the +nosimd.

Like so:

From 43d4231432838821cabe4f6aea4f0f50e87af9c4 Mon Sep 17 00:00:00 2001
From: Leif Lindholm <leif.lindholm@linaro.org>
Date: Tue, 2 Jun 2015 15:41:09 +0100
Subject: [PATCH] configure.ac: clean up arm64 soft-float handling

Fix compilation with gcc 5.1 (avoid internal compiler error), by
replacing explicit -march +nofp+nosimd options with -mgeneral-regs-only.

This also enables the removal of some further conditional build flag
setting.
---
 configure.ac | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

Comments

Leif Lindholm June 3, 2015, 11:06 a.m. UTC | #1 
On Tue, Jun 02, 2015 at 07:51:12PM +0300, Andrei Borzenkov wrote:
> > What is the relation of -mgeneral-regs-only with +nofp? The decription
> > of -mgeneral-regs-only in manual is very vague
> 
> According to
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0774a/chr1392305446662.html

That is ARM's commercial clang-based compiler suite though, not
upstream clang.
 
> 1.16 -mgeneral-regs-only
> 
> Prevents the use of floating-point instructions or floating-point registers.
> Note
> The -mgeneral-regs-only option is only valid with the aarch64-arm-none-eabi target. Use -mfpu=none to prevent the use of floating-point instructions or floating-point registers for the armv8a-arm-none-eabi target.
> 
> The description is for armclang; we can just hope that GCC is using the
> same semantic.

https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html
---
Generate code which uses only the general registers. 
---

http://clang.llvm.org/docs/UsersManual.html
---
Generate code which only uses the general purpose registers.

This option restricts the generated code to use general registers
only. This only applies to the AArch64 architecture.
---

/
    Leif
Leif Lindholm June 3, 2015, 4:52 p.m. UTC | #2 
On Wed, Jun 03, 2015 at 07:29:16PM +0300, Andrei Borzenkov wrote:
> В Wed, 3 Jun 2015 12:06:50 +0100
> Leif Lindholm <leif.lindholm@linaro.org> пишет:
> 
> > On Tue, Jun 02, 2015 at 07:51:12PM +0300, Andrei Borzenkov wrote:
> > > > What is the relation of -mgeneral-regs-only with +nofp? The decription
> > > > of -mgeneral-regs-only in manual is very vague
> > > 
> > > According to
> > > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0774a/chr1392305446662.html
> > 
> > That is ARM's commercial clang-based compiler suite though, not
> > upstream clang.
> >  
> > > 1.16 -mgeneral-regs-only
> > > 
> > > Prevents the use of floating-point instructions or floating-point registers.
> > > Note
> > > The -mgeneral-regs-only option is only valid with the aarch64-arm-none-eabi target. Use -mfpu=none to prevent the use of floating-point instructions or floating-point registers for the armv8a-arm-none-eabi target.
> > > 
> > > The description is for armclang; we can just hope that GCC is using the
> > > same semantic.
> > 
> > https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html
> > ---
> > Generate code which uses only the general registers. 
> > ---
> 
> Sure, I know this. Unfortunately it does not say how it is related to
> floating point arithmetic at all. armclang at least makes it explicit.

While it could more explicit, I am not aware of any A64 floating-point
instructions that can operate without floating-point registers.

Also, I spoke with the ARM gcc devs - the gcc documentation is
intended to be improved to also state that "-mgeneral-regs-only is
equivalent to +nofp being specified".

/
    Leif
diff mbox

Patch

diff --git a/configure.ac b/configure.ac
index 891c14f..fd8a62e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -686,9 +686,9 @@  if test x"$platform" != xemu ; then
   AC_CACHE_CHECK([for options to get soft-float], grub_cv_target_cc_soft_float, [
     grub_cv_target_cc_soft_float=no
     if test "x$target_cpu" = xarm64; then
-       CFLAGS="$TARGET_CFLAGS -march=armv8-a+nofp+nosimd -Werror"
+       CFLAGS="$TARGET_CFLAGS -mgeneral-regs-only -Werror"
        AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[]])],
-		         [grub_cv_target_cc_soft_float="-march=armv8-a+nofp+nosimd"], [])
+		         [grub_cv_target_cc_soft_float="-mgeneral-regs-only"], [])
     fi
     if test "x$target_cpu" = xia64; then
        CFLAGS="$TARGET_CFLAGS -mno-inline-float-divide -mno-inline-sqrt -Werror"
@@ -720,15 +720,7 @@  if test x"$platform" != xemu ; then
       TARGET_CFLAGS="$TARGET_CFLAGS $grub_cv_target_cc_soft_float"
       ;;
   esac
-  case x"$grub_cv_target_cc_soft_float" in
-    x"-march=armv8-a+nofp+nosimd")
-      # +nosimd disables also the cache opcodes that we need in asm.
-      TARGET_CCASFLAGS="$TARGET_CCASFLAGS -march=armv8-a+nofp"
-      ;;
-    *)
-      TARGET_CCASFLAGS="$TARGET_CCASFLAGS $grub_cv_target_cc_soft_float"
-      ;;
-  esac
+  TARGET_CCASFLAGS="$TARGET_CCASFLAGS $grub_cv_target_cc_soft_float"
 
 fi