diff mbox series

[V5,2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp

Message ID 1628754078-29779-3-git-send-email-rajpat@codeaurora.org
State New
Headers show
Series Add QSPI and QUPv3 DT nodes for SC7280 SoC | expand

Commit Message

Rajesh Patil Aug. 12, 2021, 7:41 a.m. UTC
Add spi-nor flash node and pinctrl configurations for the same.

Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

Comments

Rajesh Patil Aug. 23, 2021, 11:44 a.m. UTC | #1
On 2021-08-12 18:45, Matthias Kaehlcke wrote:
> On Thu, Aug 12, 2021 at 01:11:13PM +0530, Rajesh Patil wrote:

>> Add spi-nor flash node and pinctrl configurations for the same.

> 

> nit: better name SC7280 IDP explicitly rather than saying 'the same'.

> 


ok.I will change it

>> 

>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>

> 

> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 371a2a9..c41c2d0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -207,6 +207,20 @@ 
 	};
 };
 
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <37500000>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+	};
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
@@ -284,6 +298,19 @@ 
 
 /* PINCTRL - additions to nodes defined in sc7280.dtsi */
 
+&qspi_cs0 {
+	bias-disable;
+};
+
+&qspi_clk {
+	bias-disable;
+};
+
+&qspi_data01 {
+	/* High-Z when no transfers; nice to park the lines */
+	bias-pull-up;
+};
+
 &qup_uart5_default {
 	tx {
 		pins = "gpio46";