@@ -39,7 +39,7 @@
#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000))
#define NOC_QOS_MODEn_MASK 0x3
-static int qcom_icc_bimc_set_qos_health(struct regmap *rmap,
+static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp,
struct qcom_icc_qos *qos,
int regnum)
{
@@ -58,8 +58,8 @@ static int qcom_icc_bimc_set_qos_health(struct regmap *rmap,
mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK;
}
- return regmap_update_bits(rmap,
- M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port),
+ return regmap_update_bits(qp->regmap,
+ qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port),
mask, val);
}
@@ -85,7 +85,7 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw,
*/
if (mode != NOC_QOS_MODE_BYPASS) {
for (i = 3; i >= 0; i--) {
- rc = qcom_icc_bimc_set_qos_health(qp->regmap,
+ rc = qcom_icc_bimc_set_qos_health(qp,
&qn->qos, i);
if (rc)
return rc;
@@ -95,11 +95,12 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw,
val = 1;
}
- return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port),
+ return regmap_update_bits(qp->regmap,
+ qp->qos_offset + M_BKE_EN_ADDR(qn->qos.qos_port),
M_BKE_EN_EN_BMASK, val);
}
-static int qcom_icc_noc_set_qos_priority(struct regmap *rmap,
+static int qcom_icc_noc_set_qos_priority(struct qcom_icc_provider *qp,
struct qcom_icc_qos *qos)
{
u32 val;
@@ -107,13 +108,15 @@ static int qcom_icc_noc_set_qos_priority(struct regmap *rmap,
/* Must be updated one at a time, P1 first, P0 last */
val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT;
- rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
+ rc = regmap_update_bits(qp->regmap,
+ qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
NOC_QOS_PRIORITY_MASK, val);
if (rc)
return rc;
val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT;
- return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
+ return regmap_update_bits(qp->regmap,
+ qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
NOC_QOS_PRIORITY_MASK, val);
}
@@ -142,7 +145,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
if (mode == NOC_QOS_MODE_FIXED) {
dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n",
qn->name);
- rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos);
+ rc = qcom_icc_noc_set_qos_priority(qp, &qn->qos);
if (rc)
return rc;
} else if (mode == NOC_QOS_MODE_BYPASS) {
@@ -151,7 +154,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
}
return regmap_update_bits(qp->regmap,
- NOC_QOS_MODEn_ADDR(qn->qos.qos_port),
+ qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.qos_port),
NOC_QOS_MODEn_MASK, mode);
}
@@ -312,6 +315,7 @@ int qnoc_probe(struct platform_device *pdev)
qp->num_clks = cd_num;
qp->is_bimc_node = desc->is_bimc_node;
+ qp->qos_offset = desc->qos_offset;
if (desc->regmap_cfg) {
struct resource *res;
@@ -20,6 +20,7 @@
* @bus_clks: the clk_bulk_data table of bus clocks
* @num_clks: the total number of clk_bulk_data entries
* @is_bimc_node: indicates whether to use bimc specific setting
+ * @qos_offset: offset to QoS registers
* @regmap: regmap for QoS registers read/write access
*/
struct qcom_icc_provider {
@@ -27,6 +28,7 @@ struct qcom_icc_provider {
int num_clks;
bool is_bimc_node;
struct regmap *regmap;
+ unsigned int qos_offset;
struct clk_bulk_data bus_clks[];
};
@@ -78,6 +80,7 @@ struct qcom_icc_desc {
bool is_bimc_node;
bool has_iface_clk;
const struct regmap_config *regmap_cfg;
+ unsigned int qos_offset;
};
#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
SDM660 driver expects to have QoS registers at the beginning of NoC address space (sdm660 platform shifts NoC base address). Add support for using QoS register offset, so that other platforms do not have to change existing device trees. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/interconnect/qcom/icc-rpm.c | 24 ++++++++++++++---------- drivers/interconnect/qcom/icc-rpm.h | 3 +++ 2 files changed, 17 insertions(+), 10 deletions(-)