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[209.132.180.67]) by mx.google.com with ESMTP id al1si7329873pbc.137.2015.06.23.02.03.23 for ; Tue, 23 Jun 2015 02:03:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754575AbbFWJDW (ORCPT ); Tue, 23 Jun 2015 05:03:22 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:34295 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754571AbbFWJDN (ORCPT ); Tue, 23 Jun 2015 05:03:13 -0400 Received: by pdbki1 with SMTP id ki1so3125319pdb.1 for ; Tue, 23 Jun 2015 02:03:13 -0700 (PDT) X-Received: by 10.68.218.103 with SMTP id pf7mr66899931pbc.32.1435050192844; Tue, 23 Jun 2015 02:03:12 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.179]) by mx.google.com with ESMTPSA id or7sm22506757pdb.9.2015.06.23.02.03.06 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Jun 2015 02:03:11 -0700 (PDT) From: Jun Nie To: peter@hurleysoftware.com, linux@arm.linux.org.uk, Andrew.Jackson@arm.com, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, shawn.guo@linaro.org Cc: jason.liu@linaro.org, wan.zhijun@zte.com.cn, Jun Nie Subject: [PATCH v11 2/5] uart: pl011: Introduce register accessor Date: Tue, 23 Jun 2015 17:02:26 +0800 Message-Id: <1435050149-21153-3-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1435050149-21153-1-git-send-email-jun.nie@linaro.org> References: <1435050149-21153-1-git-send-email-jun.nie@linaro.org> Sender: linux-serial-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-serial@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jun.nie@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.51 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Introduce register accessor to ease loop up table access in later patch. Signed-off-by: Jun Nie Reviewed-by: Peter Hurley --- drivers/tty/serial/amba-pl011.c | 260 +++++++++++++++++++++------------------- 1 file changed, 140 insertions(+), 120 deletions(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index cc7d0b7..9dcc1a0 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -83,23 +83,26 @@ struct vendor_data { unsigned int (*get_fifosize)(struct amba_device *dev); }; +/* Max address offset of register in use is 0x48 */ +#define REG_NR (0x48 >> 2) +#define IDX(x) (x >> 2) enum reg_idx { - REG_DR = UART01x_DR, - REG_RSR = UART01x_RSR, - REG_ST_DMAWM = ST_UART011_DMAWM, - REG_FR = UART01x_FR, - REG_ST_LCRH_RX = ST_UART011_LCRH_RX, - REG_ILPR = UART01x_ILPR, - REG_IBRD = UART011_IBRD, - REG_FBRD = UART011_FBRD, - REG_LCRH = UART011_LCRH, - REG_CR = UART011_CR, - REG_IFLS = UART011_IFLS, - REG_IMSC = UART011_IMSC, - REG_RIS = UART011_RIS, - REG_MIS = UART011_MIS, - REG_ICR = UART011_ICR, - REG_DMACR = UART011_DMACR, + REG_DR = IDX(UART01x_DR), + REG_RSR = IDX(UART01x_RSR), + REG_ST_DMAWM = IDX(ST_UART011_DMAWM), + REG_FR = IDX(UART01x_FR), + REG_ST_LCRH_RX = IDX(ST_UART011_LCRH_RX), + REG_ILPR = IDX(UART01x_ILPR), + REG_IBRD = IDX(UART011_IBRD), + REG_FBRD = IDX(UART011_FBRD), + REG_LCRH = IDX(UART011_LCRH), + REG_CR = IDX(UART011_CR), + REG_IFLS = IDX(UART011_IFLS), + REG_IMSC = IDX(UART011_IMSC), + REG_RIS = IDX(UART011_RIS), + REG_MIS = IDX(UART011_MIS), + REG_ICR = IDX(UART011_ICR), + REG_DMACR = IDX(UART011_DMACR), }; static unsigned int get_fifosize_arm(struct amba_device *dev) @@ -190,6 +193,24 @@ struct uart_amba_port { #endif }; +static unsigned int pl011_readw(struct uart_amba_port *uap, int index) +{ + WARN_ON(index > REG_NR); + return readw_relaxed(uap->port.membase + (index << 2)); +} + +static void pl011_writew(struct uart_amba_port *uap, int val, int index) +{ + WARN_ON(index > REG_NR); + writew_relaxed(val, uap->port.membase + (index << 2)); +} + +static void pl011_writeb(struct uart_amba_port *uap, u8 val, int index) +{ + WARN_ON(index > REG_NR); + writeb_relaxed(val, uap->port.membase + (index << 2)); +} + /* * Reads up to 256 characters from the FIFO or until it's empty and * inserts them into the TTY layer. Returns the number of characters @@ -202,12 +223,12 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap) int fifotaken = 0; while (max_count--) { - status = readw(uap->port.membase + REG_FR); + status = pl011_readw(uap, REG_FR); if (status & UART01x_FR_RXFE) break; /* Take chars from the FIFO and update status */ - ch = readw(uap->port.membase + REG_DR) | + ch = pl011_readw(uap, REG_DR) | UART_DUMMY_DR_RX; flag = TTY_NORMAL; uap->port.icount.rx++; @@ -444,7 +465,7 @@ static void pl011_dma_tx_callback(void *data) dmacr = uap->dmacr; uap->dmacr = dmacr & ~UART011_TXDMAE; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); /* * If TX DMA was disabled, it means that we've stopped the DMA for @@ -558,7 +579,7 @@ static int pl011_dma_tx_refill(struct uart_amba_port *uap) dma_dev->device_issue_pending(chan); uap->dmacr |= UART011_TXDMAE; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); uap->dmatx.queued = true; /* @@ -594,9 +615,9 @@ static bool pl011_dma_tx_irq(struct uart_amba_port *uap) */ if (uap->dmatx.queued) { uap->dmacr |= UART011_TXDMAE; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); uap->im &= ~UART011_TXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); return true; } @@ -606,7 +627,7 @@ static bool pl011_dma_tx_irq(struct uart_amba_port *uap) */ if (pl011_dma_tx_refill(uap) > 0) { uap->im &= ~UART011_TXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); return true; } return false; @@ -620,7 +641,7 @@ static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) { if (uap->dmatx.queued) { uap->dmacr &= ~UART011_TXDMAE; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); } } @@ -646,14 +667,12 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) if (!uap->dmatx.queued) { if (pl011_dma_tx_refill(uap) > 0) { uap->im &= ~UART011_TXIM; - writew(uap->im, uap->port.membase + - REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); } else ret = false; } else if (!(uap->dmacr & UART011_TXDMAE)) { uap->dmacr |= UART011_TXDMAE; - writew(uap->dmacr, - uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); } return ret; } @@ -664,9 +683,9 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) */ dmacr = uap->dmacr; uap->dmacr &= ~UART011_TXDMAE; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); - if (readw(uap->port.membase + REG_FR) & UART01x_FR_TXFF) { + if (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) { /* * No space in the FIFO, so enable the transmit interrupt * so we know when there is space. Note that once we've @@ -675,13 +694,13 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) return false; } - writew(uap->port.x_char, uap->port.membase + REG_DR); + pl011_writew(uap, uap->port.x_char, REG_DR); uap->port.icount.tx++; uap->port.x_char = 0; /* Success - restore the DMA state */ uap->dmacr = dmacr; - writew(dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, dmacr, REG_DMACR); return true; } @@ -709,7 +728,7 @@ __acquires(&uap->port.lock) DMA_TO_DEVICE); uap->dmatx.queued = false; uap->dmacr &= ~UART011_TXDMAE; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); } } @@ -749,11 +768,11 @@ static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) dma_async_issue_pending(rxchan); uap->dmacr |= UART011_RXDMAE; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); uap->dmarx.running = true; uap->im &= ~UART011_RXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); return 0; } @@ -811,8 +830,9 @@ static void pl011_dma_rx_chars(struct uart_amba_port *uap, */ if (dma_count == pending && readfifo) { /* Clear any error flags */ - writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, - uap->port.membase + REG_ICR); + pl011_writew(uap, + UART011_OEIS | UART011_BEIS | UART011_PEIS + | UART011_FEIS, REG_ICR); /* * If we read all the DMA'd characters, and we had an @@ -860,7 +880,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap) /* Disable RX DMA - incoming data will wait in the FIFO */ uap->dmacr &= ~UART011_RXDMAE; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); uap->dmarx.running = false; pending = sgbuf->sg.length - state.residue; @@ -880,7 +900,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap) dev_dbg(uap->port.dev, "could not retrigger RX DMA job " "fall back to interrupt mode\n"); uap->im |= UART011_RXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); } } @@ -928,7 +948,7 @@ static void pl011_dma_rx_callback(void *data) dev_dbg(uap->port.dev, "could not retrigger RX DMA job " "fall back to interrupt mode\n"); uap->im |= UART011_RXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); } } @@ -941,7 +961,7 @@ static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) { /* FIXME. Just disable the DMA enable */ uap->dmacr &= ~UART011_RXDMAE; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); } /* @@ -985,7 +1005,7 @@ static void pl011_dma_rx_poll(unsigned long args) spin_lock_irqsave(&uap->port.lock, flags); pl011_dma_rx_stop(uap); uap->im |= UART011_RXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); spin_unlock_irqrestore(&uap->port.lock, flags); uap->dmarx.running = false; @@ -1047,7 +1067,7 @@ static void pl011_dma_startup(struct uart_amba_port *uap) skip_rx: /* Turn on DMA error (RX/TX will be enabled on demand) */ uap->dmacr |= UART011_DMAONERR; - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); /* * ST Micro variants has some specific dma burst threshold @@ -1055,8 +1075,8 @@ skip_rx: * be issued above/below 16 bytes. */ if (uap->vendor->dma_threshold) - writew(REG_ST_DMAWM_RX_16 | REG_ST_DMAWM_TX_16, - uap->port.membase + REG_ST_DMAWM); + pl011_writew(uap, REG_ST_DMAWM_RX_16 | REG_ST_DMAWM_TX_16, + REG_ST_DMAWM); if (uap->using_rx_dma) { if (pl011_dma_rx_trigger_dma(uap)) @@ -1081,12 +1101,12 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap) return; /* Disable RX and TX DMA */ - while (readw(uap->port.membase + REG_FR) & UART01x_FR_BUSY) + while (pl011_readw(uap, REG_FR) & UART01x_FR_BUSY) barrier(); spin_lock_irq(&uap->port.lock); uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); - writew(uap->dmacr, uap->port.membase + REG_DMACR); + pl011_writew(uap, uap->dmacr, REG_DMACR); spin_unlock_irq(&uap->port.lock); if (uap->using_tx_dma) { @@ -1187,7 +1207,7 @@ static void pl011_stop_tx(struct uart_port *port) container_of(port, struct uart_amba_port, port); uap->im &= ~UART011_TXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); pl011_dma_tx_stop(uap); } @@ -1197,7 +1217,7 @@ static bool pl011_tx_chars(struct uart_amba_port *uap); static void pl011_start_tx_pio(struct uart_amba_port *uap) { uap->im |= UART011_TXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); if (!uap->tx_irq_seen) pl011_tx_chars(uap); } @@ -1218,7 +1238,7 @@ static void pl011_stop_rx(struct uart_port *port) uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| UART011_PEIM|UART011_BEIM|UART011_OEIM); - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); pl011_dma_rx_stop(uap); } @@ -1229,7 +1249,7 @@ static void pl011_enable_ms(struct uart_port *port) container_of(port, struct uart_amba_port, port); uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); } static void pl011_rx_chars(struct uart_amba_port *uap) @@ -1249,7 +1269,7 @@ __acquires(&uap->port.lock) dev_dbg(uap->port.dev, "could not trigger RX DMA job " "fall back to interrupt mode again\n"); uap->im |= UART011_RXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); } else { #ifdef CONFIG_DMA_ENGINE /* Start Rx DMA poll */ @@ -1275,13 +1295,13 @@ __acquires(&uap->port.lock) */ static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c) { - writew(c, uap->port.membase + REG_DR); + pl011_writew(uap, c, REG_DR); uap->port.icount.tx++; if (likely(uap->tx_irq_seen > 1)) return true; - return !(readw(uap->port.membase + REG_FR) & UART01x_FR_TXFF); + return !(pl011_readw(uap, REG_FR) & UART01x_FR_TXFF); } static bool pl011_tx_chars(struct uart_amba_port *uap) @@ -1311,7 +1331,7 @@ static bool pl011_tx_chars(struct uart_amba_port *uap) * and can't transmit immediately in any case: */ if (unlikely(uap->tx_irq_seen < 2 && - readw(uap->port.membase + REG_FR) & UART01x_FR_TXFF)) + pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)) return false; if (uap->port.x_char) { @@ -1353,7 +1373,7 @@ static void pl011_modem_status(struct uart_amba_port *uap) { unsigned int status, delta; - status = readw(uap->port.membase + REG_FR) & UART01x_FR_MODEM_ANY; + status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY; delta = status ^ uap->old_status; uap->old_status = status; @@ -1404,25 +1424,24 @@ static irqreturn_t pl011_int(int irq, void *dev_id) unsigned int dummy_read; spin_lock_irqsave(&uap->port.lock, flags); - status = readw(uap->port.membase + REG_MIS); + status = pl011_readw(uap, REG_MIS); if (status) { do { if (uap->vendor->cts_event_workaround) { /* workaround to make sure that all bits are unlocked.. */ - writew(0x00, uap->port.membase + REG_ICR); + pl011_writew(uap, 0x00, REG_ICR); /* * WA: introduce 26ns(1 uart clk) delay before W1C; * single apb access will incur 2 pclk(133.12Mhz) delay, * so add 2 dummy reads */ - dummy_read = readw(uap->port.membase + REG_ICR); - dummy_read = readw(uap->port.membase + REG_ICR); + dummy_read = pl011_readw(uap, REG_ICR); + dummy_read = pl011_readw(uap, REG_ICR); } - writew(status & ~(UART011_TXIS|UART011_RTIS| - UART011_RXIS), - uap->port.membase + REG_ICR); + pl011_writew(uap, status & ~(UART011_TXIS|UART011_RTIS| + UART011_RXIS), REG_ICR); if (status & (UART011_RTIS|UART011_RXIS)) { if (pl011_dma_rx_running(uap)) @@ -1441,7 +1460,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id) if (pass_counter-- == 0) break; - status = readw(uap->port.membase + REG_MIS); + status = pl011_readw(uap, REG_MIS); } while (status != 0); handled = 1; } @@ -1455,7 +1474,7 @@ static unsigned int pl011_tx_empty(struct uart_port *port) { struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); - unsigned int status = readw(uap->port.membase + REG_FR); + unsigned int status = pl011_readw(uap, REG_FR); return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; } @@ -1464,7 +1483,7 @@ static unsigned int pl011_get_mctrl(struct uart_port *port) struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); unsigned int result = 0; - unsigned int status = readw(uap->port.membase + REG_FR); + unsigned int status = pl011_readw(uap, REG_FR); #define TIOCMBIT(uartbit, tiocmbit) \ if (status & uartbit) \ @@ -1484,7 +1503,7 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) container_of(port, struct uart_amba_port, port); unsigned int cr; - cr = readw(uap->port.membase + REG_CR); + cr = pl011_readw(uap, REG_CR); #define TIOCMBIT(tiocmbit, uartbit) \ if (mctrl & tiocmbit) \ @@ -1504,7 +1523,7 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) } #undef TIOCMBIT - writew(cr, uap->port.membase + REG_CR); + pl011_writew(uap, cr, REG_CR); } static void pl011_break_ctl(struct uart_port *port, int break_state) @@ -1515,12 +1534,12 @@ static void pl011_break_ctl(struct uart_port *port, int break_state) unsigned int lcr_h; spin_lock_irqsave(&uap->port.lock, flags); - lcr_h = readw(uap->port.membase + uap->lcrh_tx); + lcr_h = pl011_readw(uap, uap->lcrh_tx); if (break_state == -1) lcr_h |= UART01x_LCRH_BRK; else lcr_h &= ~UART01x_LCRH_BRK; - writew(lcr_h, uap->port.membase + uap->lcrh_tx); + pl011_writew(uap, lcr_h, uap->lcrh_tx); spin_unlock_irqrestore(&uap->port.lock, flags); } @@ -1530,9 +1549,8 @@ static void pl011_quiesce_irqs(struct uart_port *port) { struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); - unsigned char __iomem *regs = uap->port.membase; - writew(readw(regs + REG_MIS), regs + REG_ICR); + pl011_writew(uap, pl011_readw(uap, REG_MIS), REG_ICR); /* * There is no way to clear TXIM as this is "ready to transmit IRQ", so * we simply mask it. start_tx() will unmask it. @@ -1546,7 +1564,7 @@ static void pl011_quiesce_irqs(struct uart_port *port) * (including tx queue), so we're also fine with start_tx()'s caller * side. */ - writew(readw(regs + REG_IMSC) & ~UART011_TXIM, regs + REG_IMSC); + pl011_writew(uap, pl011_readw(uap, REG_IMSC) & ~UART011_TXIM, REG_IMSC); } static int pl011_get_poll_char(struct uart_port *port) @@ -1561,11 +1579,11 @@ static int pl011_get_poll_char(struct uart_port *port) */ pl011_quiesce_irqs(port); - status = readw(uap->port.membase + REG_FR); + status = pl011_readw(uap, REG_FR); if (status & UART01x_FR_RXFE) return NO_POLL_CHAR; - return readw(uap->port.membase + REG_DR); + return pl011_readw(uap, REG_DR); } static void pl011_put_poll_char(struct uart_port *port, @@ -1574,10 +1592,10 @@ static void pl011_put_poll_char(struct uart_port *port, struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); - while (readw(uap->port.membase + REG_FR) & UART01x_FR_TXFF) + while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) barrier(); - writew(ch, uap->port.membase + REG_DR); + pl011_writew(uap, ch, REG_DR); } #endif /* CONFIG_CONSOLE_POLL */ @@ -1601,15 +1619,15 @@ static int pl011_hwinit(struct uart_port *port) uap->port.uartclk = clk_get_rate(uap->clk); /* Clear pending error and receive interrupts */ - writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS | - UART011_RTIS | UART011_RXIS, uap->port.membase + REG_ICR); + pl011_writew(uap, UART011_OEIS | UART011_BEIS | UART011_PEIS | + UART011_FEIS | UART011_RTIS | UART011_RXIS, REG_ICR); /* * Save interrupts enable mask, and enable RX interrupts in case if * the interrupt is used for NMI entry. */ - uap->im = readw(uap->port.membase + REG_IMSC); - writew(UART011_RTIM | UART011_RXIM, uap->port.membase + REG_IMSC); + uap->im = pl011_readw(uap, REG_IMSC); + pl011_writew(uap, UART011_RTIM | UART011_RXIM, REG_IMSC); if (dev_get_platdata(uap->port.dev)) { struct amba_pl011_data *plat; @@ -1623,7 +1641,7 @@ static int pl011_hwinit(struct uart_port *port) static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) { - writew(lcr_h, uap->port.membase + uap->lcrh_rx); + pl011_writew(uap, lcr_h, uap->lcrh_rx); if (uap->lcrh_rx != uap->lcrh_tx) { int i; /* @@ -1631,8 +1649,8 @@ static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) * to get this delay write read only register 10 times */ for (i = 0; i < 10; ++i) - writew(0xff, uap->port.membase + REG_MIS); - writew(lcr_h, uap->port.membase + uap->lcrh_tx); + pl011_writew(uap, 0xff, REG_MIS); + pl011_writew(uap, lcr_h, uap->lcrh_tx); } } @@ -1647,7 +1665,7 @@ static int pl011_startup(struct uart_port *port) if (retval) goto clk_dis; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); /* * Allocate the IRQ @@ -1656,7 +1674,7 @@ static int pl011_startup(struct uart_port *port) if (retval) goto clk_dis; - writew(uap->vendor->ifls, uap->port.membase + REG_IFLS); + pl011_writew(uap, uap->vendor->ifls, REG_IFLS); /* Assume that TX IRQ doesn't work until we see one: */ uap->tx_irq_seen = 0; @@ -1666,14 +1684,14 @@ static int pl011_startup(struct uart_port *port) /* restore RTS and DTR */ cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; - writew(cr, uap->port.membase + REG_CR); + pl011_writew(uap, cr, REG_CR); spin_unlock_irq(&uap->port.lock); /* * initialise the old status of the modem signals */ - uap->old_status = readw(uap->port.membase + REG_FR) & UART01x_FR_MODEM_ANY; + uap->old_status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY; /* Startup DMA */ pl011_dma_startup(uap); @@ -1685,12 +1703,11 @@ static int pl011_startup(struct uart_port *port) */ spin_lock_irq(&uap->port.lock); /* Clear out any spuriously appearing RX interrupts */ - writew(UART011_RTIS | UART011_RXIS, - uap->port.membase + REG_ICR); + pl011_writew(uap, UART011_RTIS | UART011_RXIS, REG_ICR); uap->im = UART011_RTIM; if (!pl011_dma_rx_running(uap)) uap->im |= UART011_RXIM; - writew(uap->im, uap->port.membase + REG_IMSC); + pl011_writew(uap, uap->im, REG_IMSC); spin_unlock_irq(&uap->port.lock); return 0; @@ -1703,11 +1720,11 @@ static int pl011_startup(struct uart_port *port) static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh) { - unsigned long val; + unsigned long val; - val = readw(uap->port.membase + lcrh); - val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); - writew(val, uap->port.membase + lcrh); + val = pl011_readw(uap, lcrh); + val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); + pl011_writew(uap, val, lcrh); } static void pl011_shutdown(struct uart_port *port) @@ -1723,8 +1740,8 @@ static void pl011_shutdown(struct uart_port *port) */ spin_lock_irq(&uap->port.lock); uap->im = 0; - writew(uap->im, uap->port.membase + REG_IMSC); - writew(0xffff, uap->port.membase + REG_ICR); + pl011_writew(uap, uap->im, REG_IMSC); + pl011_writew(uap, 0xffff, REG_ICR); spin_unlock_irq(&uap->port.lock); pl011_dma_shutdown(uap); @@ -1742,11 +1759,11 @@ static void pl011_shutdown(struct uart_port *port) */ uap->autorts = false; spin_lock_irq(&uap->port.lock); - cr = readw(uap->port.membase + REG_CR); + cr = pl011_readw(uap, REG_CR); uap->old_cr = cr; cr &= UART011_CR_RTS | UART011_CR_DTR; cr |= UART01x_CR_UARTEN | UART011_CR_TXE; - writew(cr, uap->port.membase + REG_CR); + pl011_writew(uap, cr, REG_CR); spin_unlock_irq(&uap->port.lock); /* @@ -1871,8 +1888,8 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, pl011_enable_ms(port); /* first, disable everything */ - old_cr = readw(port->membase + REG_CR); - writew(0, port->membase + REG_CR); + old_cr = pl011_readw(uap, REG_CR); + pl011_writew(uap, 0, REG_CR); if (termios->c_cflag & CRTSCTS) { if (old_cr & UART011_CR_RTS) @@ -1905,8 +1922,8 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, quot -= 2; } /* Set baud rate */ - writew(quot & 0x3f, port->membase + REG_FBRD); - writew(quot >> 6, port->membase + REG_IBRD); + pl011_writew(uap, quot & 0x3f, REG_FBRD); + pl011_writew(uap, quot >> 6, REG_IBRD); /* * ----------v----------v----------v----------v----- @@ -1915,7 +1932,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, * ----------^----------^----------^----------^----- */ pl011_write_lcr_h(uap, lcr_h); - writew(old_cr, port->membase + REG_CR); + pl011_writew(uap, old_cr, REG_CR); spin_unlock_irqrestore(&port->lock, flags); } @@ -2004,9 +2021,9 @@ static void pl011_console_putchar(struct uart_port *port, int ch) struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); - while (readw(uap->port.membase + REG_FR) & UART01x_FR_TXFF) + while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) barrier(); - writew(ch, uap->port.membase + REG_DR); + pl011_writew(uap, ch, REG_DR); } static void @@ -2030,10 +2047,10 @@ pl011_console_write(struct console *co, const char *s, unsigned int count) /* * First save the CR then disable the interrupts */ - old_cr = readw(uap->port.membase + REG_CR); + old_cr = pl011_readw(uap, REG_CR); new_cr = old_cr & ~UART011_CR_CTSEN; new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; - writew(new_cr, uap->port.membase + REG_CR); + pl011_writew(uap, new_cr, REG_CR); uart_console_write(&uap->port, s, count, pl011_console_putchar); @@ -2042,9 +2059,9 @@ pl011_console_write(struct console *co, const char *s, unsigned int count) * and restore the TCR */ do { - status = readw(uap->port.membase + REG_FR); + status = pl011_readw(uap, REG_FR); } while (status & UART01x_FR_BUSY); - writew(old_cr, uap->port.membase + REG_CR); + pl011_writew(uap, old_cr, REG_CR); if (locked) spin_unlock(&uap->port.lock); @@ -2057,10 +2074,10 @@ static void __init pl011_console_get_options(struct uart_amba_port *uap, int *baud, int *parity, int *bits) { - if (readw(uap->port.membase + REG_CR) & UART01x_CR_UARTEN) { + if (pl011_readw(uap, REG_CR) & UART01x_CR_UARTEN) { unsigned int lcr_h, ibrd, fbrd; - lcr_h = readw(uap->port.membase + uap->lcrh_tx); + lcr_h = pl011_readw(uap, uap->lcrh_tx); *parity = 'n'; if (lcr_h & UART01x_LCRH_PEN) { @@ -2075,13 +2092,13 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud, else *bits = 8; - ibrd = readw(uap->port.membase + REG_IBRD); - fbrd = readw(uap->port.membase + REG_FBRD); + ibrd = pl011_readw(uap, REG_IBRD); + fbrd = pl011_readw(uap, REG_FBRD); *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); if (uap->vendor->oversampling) { - if (readw(uap->port.membase + REG_CR) + if (pl011_readw(uap, REG_CR) & ST_UART011_CR_OVSFACT) *baud *= 2; } @@ -2148,10 +2165,13 @@ static struct console amba_console = { static void pl011_putc(struct uart_port *port, int c) { - while (readl(port->membase + REG_FR) & UART01x_FR_TXFF) + struct uart_amba_port *uap = + container_of(port, struct uart_amba_port, port); + + while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) ; - writeb(c, port->membase + REG_DR); - while (readl(port->membase + REG_FR) & UART01x_FR_BUSY) + pl011_writeb(uap, c, REG_DR); + while (pl011_readw(uap, REG_FR) & UART01x_FR_BUSY) ; } @@ -2267,8 +2287,8 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) INIT_DELAYED_WORK(&uap->tx_softirq_work, pl011_tx_softirq); /* Ensure interrupts from this UART are masked and cleared */ - writew(0, uap->port.membase + REG_IMSC); - writew(0xffff, uap->port.membase + REG_ICR); + pl011_writew(uap, 0, REG_IMSC); + pl011_writew(uap, 0xffff, REG_ICR); snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));