| Message ID | 20210830041729.237252-10-anup.patel@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Linux RISC-V ACLINT Support | expand |
On Mon, Aug 30, 2021 at 09:47:27AM +0530, Anup Patel wrote: > We add DT bindings documentation for the ACLINT MTIMER device > found on RISC-V SOCs. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > --- > .../bindings/timer/riscv,aclint-mtimer.yaml | 70 +++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml > > diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml > new file mode 100644 > index 000000000000..b0b2ee6c761c > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V ACLINT M-level Timer > + > +maintainers: > + - Anup Patel <anup.patel@wdc.com> > + > +description: > + RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined > + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The > + ACLINT MTIMER device is documented in the RISC-V ACLINT specification found > + at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. > + > + The ACLINT MTIMER device directly connects to the M-level timer interrupt > + lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local > + interrupt controller is the parent interrupt controller for the ACLINT > + MTIMER device. > + > + The clock frequency of ACLINT is specified via "timebase-frequency" DT > + property of "/cpus" DT node. The "timebase-frequency" DT property is > + described in Documentation/devicetree/bindings/riscv/cpus.yaml > + > +properties: > + compatible: > + enum: > + - riscv,aclint-mtimer > + > + description: > + Should be "riscv,aclint-mtimer" or "<vendor>,<chip>-aclint-mtimer". Again, should be AND. > + > + reg: > + description: | > + Specifies base physical address(s) of the MTIME register and MTIMECMPx > + registers. The 1st region is the MTIME register base and size. The 2nd > + region is the MTIMECMPx registers base and size. > + minItems: 2 > + maxItems: 2 > + > + interrupts-extended: > + minItems: 1 > + maxItems: 4095 > + > + mtimer,no-64bit-mmio: > + type: boolean > + description: If present, the timer does not support 64-bit MMIO accesses > + for both MTIME and MTIMECMP registers. This should be implied by the compatible. > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts-extended > + > +examples: > + - | > + timer@2000000 { > + compatible = "riscv,aclint-mtimer"; > + reg = <0x2000000 0x8>, > + <0x2004000 0x7ff8>; > + interrupts-extended = <&cpu1intc 7>, > + <&cpu2intc 7>, > + <&cpu3intc 7>, > + <&cpu4intc 7>; > + }; > +... > -- > 2.25.1 > >
diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml new file mode 100644 index 000000000000..b0b2ee6c761c --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V ACLINT M-level Timer + +maintainers: + - Anup Patel <anup.patel@wdc.com> + +description: + RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The + ACLINT MTIMER device is documented in the RISC-V ACLINT specification found + at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc. + + The ACLINT MTIMER device directly connects to the M-level timer interrupt + lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local + interrupt controller is the parent interrupt controller for the ACLINT + MTIMER device. + + The clock frequency of ACLINT is specified via "timebase-frequency" DT + property of "/cpus" DT node. The "timebase-frequency" DT property is + described in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + enum: + - riscv,aclint-mtimer + + description: + Should be "riscv,aclint-mtimer" or "<vendor>,<chip>-aclint-mtimer". + + reg: + description: | + Specifies base physical address(s) of the MTIME register and MTIMECMPx + registers. The 1st region is the MTIME register base and size. The 2nd + region is the MTIMECMPx registers base and size. + minItems: 2 + maxItems: 2 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + + mtimer,no-64bit-mmio: + type: boolean + description: If present, the timer does not support 64-bit MMIO accesses + for both MTIME and MTIMECMP registers. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@2000000 { + compatible = "riscv,aclint-mtimer"; + reg = <0x2000000 0x8>, + <0x2004000 0x7ff8>; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + }; +...