| Message ID | 1630406202-3919-1-git-send-email-tdas@codeaurora.org |
|---|---|
| State | Accepted |
| Commit | d15eb8012476fa49cdd14f932d302a352f213f87 |
| Headers | show |
| Series | [v1,1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 | expand |
On Tue, Aug 31, 2021 at 04:06:41PM +0530, Taniya Das wrote: > The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic > properties that are needed in a device tree. Add the LPASS clock IDs for > LPASS PIL client to request for the clocks. > > Signed-off-by: Taniya Das <tdas@codeaurora.org> > --- > .../bindings/clock/qcom,sc7280-lpasscc.yaml | 69 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,lpass-sc7280.h | 16 +++++ > 2 files changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml > create mode 100644 include/dt-bindings/clock/qcom,lpass-sc7280.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml > new file mode 100644 > index 0000000..7b62763 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml > @@ -0,0 +1,69 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm LPASS Core Clock Controller Binding for SC7280 > + > +maintainers: > + - Taniya Das <tdas@codeaurora.org> > + > +description: | > + Qualcomm LPASS core clock control module which supports the clocks and > + power domains on SC7280. > + > + See also: > + - dt-bindings/clock/qcom,lpass-sc7280.h > + > +properties: > + compatible: > + enum: > + - qcom,sc7280-lpasscc > + > + clocks: > + items: > + - description: gcc_cfg_noc_lpass_clk from GCC > + > + clock-names: > + items: > + - const: iface > + > + '#clock-cells': > + const: 1 > + > + reg: > + minItems: 3 Don't need minItems equal to 'items' length. > + items: > + - description: LPASS qdsp6ss register > + - description: LPASS top-cc register > + - description: LPASS cc register > + > + reg-names: > + items: > + - const: qdsp6ss > + - const: top_cc > + - const: cc > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > + #include <dt-bindings/clock/qcom,lpass-sc7280.h> > + clock-controller@3000000 { > + compatible = "qcom,sc7280-lpasscc"; > + reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; > + reg-names = "qdsp6ss", "top_cc", "cc"; > + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; > + clock-names = "iface"; > + #clock-cells = <1>; > + }; > +... > diff --git a/include/dt-bindings/clock/qcom,lpass-sc7280.h b/include/dt-bindings/clock/qcom,lpass-sc7280.h > new file mode 100644 > index 0000000..a259463 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,lpass-sc7280.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Dual license. > +/* > + * Copyright (c) 2021, The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H > +#define _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H > + > +#define LPASS_Q6SS_AHBM_CLK 0 > +#define LPASS_Q6SS_AHBS_CLK 1 > +#define LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK 2 > +#define LPASS_QDSP6SS_XO_CLK 3 > +#define LPASS_QDSP6SS_SLEEP_CLK 4 > +#define LPASS_QDSP6SS_CORE_CLK 5 > + > +#endif > -- > Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member > of the Code Aurora Forum, hosted by the Linux Foundation. > >
Quoting Taniya Das (2021-08-31 03:36:42) > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 0a55967..cd7a5a1 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -394,6 +394,14 @@ config SC_LPASS_CORECC_7180 > Say Y if you want to use LPASS clocks and power domains of the LPASS > core clock controller. > > +config SC_LPASSCC_7280 > + tristate "SC7280 Low Power Audio Subsystem (LPAAS) Clock Controller" > + select SC_GCC_7280 > + help > + Support for the LPASS clock controller on SC7280 devices. > + Say Y if you want to use the LPASS branch clocks of the LPASS clock > + controller to reset the LPASS subsystem. > + Can you send another patch to move SC_LPASS_CORECC_7180 under SC_GPUCC_7180? This file should be sorted on Kconfig symbol alphabetically. > config SC_GPUCC_7180 > tristate "SC7180 Graphics Clock Controller" > select SC_GCC_7180 > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 9825ef8..1b33f49 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -66,6 +66,7 @@ obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o > obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o > obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o > obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o > +obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o This one got it right, almost. LPASSCC comes before LPASS_CORECC though. > obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o > obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o > obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml new file mode 100644 index 0000000..7b62763 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7280 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7280. + + See also: + - dt-bindings/clock/qcom,lpass-sc7280.h + +properties: + compatible: + enum: + - qcom,sc7280-lpasscc + + clocks: + items: + - description: gcc_cfg_noc_lpass_clk from GCC + + clock-names: + items: + - const: iface + + '#clock-cells': + const: 1 + + reg: + minItems: 3 + items: + - description: LPASS qdsp6ss register + - description: LPASS top-cc register + - description: LPASS cc register + + reg-names: + items: + - const: qdsp6ss + - const: top_cc + - const: cc + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpass-sc7280.h> + clock-controller@3000000 { + compatible = "qcom,sc7280-lpasscc"; + reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; + reg-names = "qdsp6ss", "top_cc", "cc"; + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,lpass-sc7280.h b/include/dt-bindings/clock/qcom,lpass-sc7280.h new file mode 100644 index 0000000..a259463 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpass-sc7280.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H + +#define LPASS_Q6SS_AHBM_CLK 0 +#define LPASS_Q6SS_AHBS_CLK 1 +#define LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Add the LPASS clock IDs for LPASS PIL client to request for the clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- .../bindings/clock/qcom,sc7280-lpasscc.yaml | 69 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,lpass-sc7280.h | 16 +++++ 2 files changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpass-sc7280.h