| Message ID | 20210910184147.336618-19-paul.kocialkowski@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | [01/22] clk: sunxi-ng: v3s: Make the ISP PLL clock public | expand |
diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml index c60f6b5403fa..9f796cd89a2f 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml @@ -104,6 +104,20 @@ properties: additionalProperties: false + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + description: ISP output port + + properties: + reg: + const: 2 + + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + additionalProperties: false + required: - compatible - reg
Some Allwinner devices come with an Image Signal Processor (ISP) that allows processing camera data to produce good-looking images, especially from raw bayer representations. The ISP does not have a dedicated capture path: it is fed directly by one of the CSI controllers, which can be selected at run-time. Represent this possibility as a graph connection between the CSI controller and the ISP in the device-tree bindings. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> --- .../bindings/media/allwinner,sun6i-a31-csi.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+)