| Message ID | 20210915205809.59068-1-shashi.mallela@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | hw/intc: GIC maintenance interrupt not triggered | expand |
On 9/15/21 10:58 PM, Shashi Mallela wrote: > During sbsa acs level 3 testing,it is seen that the GIC > maintenance interrupts are not triggered and the related test > cases failed.On debugging the cause,found that the value of > MISR register (from maintenance_interrupt_state()) was being > passed to qemu_set_irq() as level.Updated logic to set level > to 1 if any of the maintenance interrupt attributes are set. > Confirmed that the GIC maintanence interrupts are triggered and > sbsa acs test cases passed with this change. > Fixes: c5fc89b36c0 ("hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()") > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> > --- > hw/intc/arm_gicv3_cpuif.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c > index 462a35f66e..34691d4fe2 100644 > --- a/hw/intc/arm_gicv3_cpuif.c > +++ b/hw/intc/arm_gicv3_cpuif.c > @@ -418,7 +418,9 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) > } > > if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) { > - maintlevel = maintenance_interrupt_state(cs); > + if (maintenance_interrupt_state(cs)) { > + maintlevel = 1; > + } Or: maintlevel = !!maintenance_interrupt_state(cs); But your style is more explicit. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On Thu, 16 Sept 2021 at 05:36, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > On 9/15/21 10:58 PM, Shashi Mallela wrote: > > During sbsa acs level 3 testing,it is seen that the GIC > > maintenance interrupts are not triggered and the related test > > cases failed.On debugging the cause,found that the value of > > MISR register (from maintenance_interrupt_state()) was being > > passed to qemu_set_irq() as level.Updated logic to set level > > to 1 if any of the maintenance interrupt attributes are set. > > Confirmed that the GIC maintanence interrupts are triggered and > > sbsa acs test cases passed with this change. > > > > Fixes: c5fc89b36c0 ("hw/intc/arm_gicv3: Implement > gicv3_cpuif_virt_update()") > > > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> > > --- > > hw/intc/arm_gicv3_cpuif.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c > > index 462a35f66e..34691d4fe2 100644 > > --- a/hw/intc/arm_gicv3_cpuif.c > > +++ b/hw/intc/arm_gicv3_cpuif.c > > @@ -418,7 +418,9 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) > > } > > > > if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) { > > - maintlevel = maintenance_interrupt_state(cs); > > + if (maintenance_interrupt_state(cs)) { > > + maintlevel = 1; > > + } > > Or: > maintlevel = !!maintenance_interrupt_state(cs); > > But your style is more explicit. Applied to target-arm.next, thanks. I opted to tweak the code to + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) && + maintenance_interrupt_state(cs) != 0) { + maintlevel = 1; } to avoid the nested if()s. -- PMM
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 462a35f66e..34691d4fe2 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -418,7 +418,9 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) } if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) { - maintlevel = maintenance_interrupt_state(cs); + if (maintenance_interrupt_state(cs)) { + maintlevel = 1; + } } trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,
During sbsa acs level 3 testing,it is seen that the GIC maintenance interrupts are not triggered and the related test cases failed.On debugging the cause,found that the value of MISR register (from maintenance_interrupt_state()) was being passed to qemu_set_irq() as level.Updated logic to set level to 1 if any of the maintenance interrupt attributes are set. Confirmed that the GIC maintanence interrupts are triggered and sbsa acs test cases passed with this change. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> --- hw/intc/arm_gicv3_cpuif.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.27.0