| Message ID | 1631643550-29960-4-git-send-email-pmaliset@codeaurora.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add DT bindings and DT nodes for PCIe and PHY in SC7280 | expand |
Quoting Prasad Malisetty (2021-09-14 11:19:09) > Enable PCIe controller and PHY for sc7280 IDP board. > Add specific NVMe GPIO entries for SKU1 and SKU2 support. > > Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 9 +++++++++ > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 32 ++++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 9 +++++++++ > 3 files changed, 50 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > index 64fc22a..2cc6b0a 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > @@ -61,6 +61,15 @@ > modem-init; > }; > > +&pcie1_default_state { > + nvme-n { > + pins = "gpio19"; > + function = "gpio"; > + > + bias-pull-up; > + }; I don't think the style is to have a single container node anymore. Instead, each pin gets a different node and then pinctrl-0 has a list of phandles to the different nodes. qcom maintainers may have more input here. Also, this should really go into a different section than here. I thought the style was to have a 'board specific' pinctrl section. > +}; > + > &pmk8350_vadc { > pmr735a_die_temp { > reg = <PMR735A_ADC7_DIE_TEMP>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 64fc22a..2cc6b0a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -61,6 +61,15 @@ modem-init; }; +&pcie1_default_state { + nvme-n { + pins = "gpio19"; + function = "gpio"; + + bias-pull-up; + }; +}; + &pmk8350_vadc { pmr735a_die_temp { reg = <PMR735A_ADC7_DIE_TEMP>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 371a2a9..e73a7c2 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -199,6 +199,38 @@ modem-init; }; +&pcie1 { + status = "okay"; + + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + +&pcie1_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l10c_0p8>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + +&pcie1_default_state { + reset-n { + pins = "gpio2"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-disable; + }; + + wake-n { + pins = "gpio3"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; +}; + &pmk8350_vadc { pmk8350_die_temp { reg = <PMK8350_ADC7_DIE_TEMP>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts index 1fc2add..8432afc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts @@ -21,3 +21,12 @@ stdout-path = "serial0:115200n8"; }; }; + +&pcie1_default_state { + nvme-n { + pins = "gpio51"; + function = "gpio"; + + bias-pull-up; + }; +};
Enable PCIe controller and PHY for sc7280 IDP board. Add specific NVMe GPIO entries for SKU1 and SKU2 support. Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 9 +++++++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 32 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 9 +++++++++ 3 files changed, 50 insertions(+)