| Message ID | 20211007070900.456044-10-vkoul@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
On 07/10/2021 10:08, Vinod Koul wrote: > For DSC to work we typically need a 2,2,1 configuration. This should > suffice for resolutions upto 4k. For more resolutions like 8k this won't > work. > > Also, it is better to use 2 LMs and DSC instances as half width results > in lesser power consumption as compared to single LM, DSC at full width. > > The panel has been tested only with 2,2,1 configuration, so for > now we blindly create 2,2,1 topology when DSC is enabled > > Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org> > Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- > Changes since > RFC: > - Add more details in changelog > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index aac51c1bdf94..70f57a071165 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -538,6 +538,8 @@ static struct msm_display_topology dpu_encoder_get_topology( > struct drm_display_mode *mode) > { > struct msm_display_topology topology = {0}; > + struct drm_encoder *drm_enc; > + struct msm_drm_private *priv; > int i, intf_count = 0; > > for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) > @@ -572,8 +574,22 @@ static struct msm_display_topology dpu_encoder_get_topology( > topology.num_enc = 0; > topology.num_intf = intf_count; > > + drm_enc = &dpu_enc->base; > + priv = drm_enc->dev->dev_private; > + if (priv && priv->dsc) { > + /* In case of Display Stream Compression DSC, we would use > + * 2 encoders, 2 line mixers and 1 interface > + * this is power optimal and can drive upto (including) 4k > + * screens > + */ > + topology.num_enc = 2; > + topology.num_intf = 1; > + topology.num_lm = 2; So, here you'd set the topology.num_rm. > + } > + > return topology; > } > + > static int dpu_encoder_virt_atomic_check( > struct drm_encoder *drm_enc, > struct drm_crtc_state *crtc_state, > -- With best wishes Dmitry
On 14/10/2021 17:13, Dmitry Baryshkov wrote: > On 07/10/2021 10:08, Vinod Koul wrote: >> For DSC to work we typically need a 2,2,1 configuration. This should >> suffice for resolutions upto 4k. For more resolutions like 8k this won't >> work. >> >> Also, it is better to use 2 LMs and DSC instances as half width results >> in lesser power consumption as compared to single LM, DSC at full width. >> >> The panel has been tested only with 2,2,1 configuration, so for >> now we blindly create 2,2,1 topology when DSC is enabled >> >> Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org> >> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> >> Signed-off-by: Vinod Koul <vkoul@kernel.org> >> --- >> Changes since >> RFC: >> - Add more details in changelog >> >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> index aac51c1bdf94..70f57a071165 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c >> @@ -538,6 +538,8 @@ static struct msm_display_topology >> dpu_encoder_get_topology( >> struct drm_display_mode *mode) >> { >> struct msm_display_topology topology = {0}; >> + struct drm_encoder *drm_enc; >> + struct msm_drm_private *priv; >> int i, intf_count = 0; >> for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) >> @@ -572,8 +574,22 @@ static struct msm_display_topology >> dpu_encoder_get_topology( >> topology.num_enc = 0; >> topology.num_intf = intf_count; >> + drm_enc = &dpu_enc->base; >> + priv = drm_enc->dev->dev_private; >> + if (priv && priv->dsc) { >> + /* In case of Display Stream Compression DSC, we would use >> + * 2 encoders, 2 line mixers and 1 interface >> + * this is power optimal and can drive upto (including) 4k >> + * screens >> + */ >> + topology.num_enc = 2; >> + topology.num_intf = 1; >> + topology.num_lm = 2; > > So, here you'd set the topology.num_rm. I meant 'num_dsc', please excuse the typo. > >> + } >> + >> return topology; >> } >> + >> static int dpu_encoder_virt_atomic_check( >> struct drm_encoder *drm_enc, >> struct drm_crtc_state *crtc_state, >> > > -- With best wishes Dmitry
On 25-10-21, 17:37, Dmitry Baryshkov wrote: > On 14/10/2021 17:13, Dmitry Baryshkov wrote: > > On 07/10/2021 10:08, Vinod Koul wrote: > > > @@ -572,8 +574,22 @@ static struct msm_display_topology > > > dpu_encoder_get_topology( > > > topology.num_enc = 0; > > > topology.num_intf = intf_count; > > > + drm_enc = &dpu_enc->base; > > > + priv = drm_enc->dev->dev_private; > > > + if (priv && priv->dsc) { > > > + /* In case of Display Stream Compression DSC, we would use > > > + * 2 encoders, 2 line mixers and 1 interface > > > + * this is power optimal and can drive upto (including) 4k > > > + * screens > > > + */ > > > + topology.num_enc = 2; > > > + topology.num_intf = 1; > > > + topology.num_lm = 2; > > > > So, here you'd set the topology.num_rm. > > I meant 'num_dsc', please excuse the typo. No worries, i had assumed such and made it num_dsc -- ~Vinod
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index aac51c1bdf94..70f57a071165 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -538,6 +538,8 @@ static struct msm_display_topology dpu_encoder_get_topology( struct drm_display_mode *mode) { struct msm_display_topology topology = {0}; + struct drm_encoder *drm_enc; + struct msm_drm_private *priv; int i, intf_count = 0; for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) @@ -572,8 +574,22 @@ static struct msm_display_topology dpu_encoder_get_topology( topology.num_enc = 0; topology.num_intf = intf_count; + drm_enc = &dpu_enc->base; + priv = drm_enc->dev->dev_private; + if (priv && priv->dsc) { + /* In case of Display Stream Compression DSC, we would use + * 2 encoders, 2 line mixers and 1 interface + * this is power optimal and can drive upto (including) 4k + * screens + */ + topology.num_enc = 2; + topology.num_intf = 1; + topology.num_lm = 2; + } + return topology; } + static int dpu_encoder_virt_atomic_check( struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,