[v4,7/9] ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board.

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9908b43..767f0d8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -735,6 +735,13 @@  config TARGET_LS2085ARDB
 	  development platform that supports the QorIQ LS2085A
 	  Layerscape Architecture processor.
 
+config TARGET_HIKEY
+	bool "Support HiKey 96boards Consumer Edition Platform"
+	select ARM64
+	  help
+	  Support for HiKey 96boards platform. It features a HI6220
+	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -880,6 +887,7 @@  source "board/Marvell/gplugd/Kconfig"
 source "board/armadeus/apf27/Kconfig"
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
+source "board/hisilicon/hikey/Kconfig"
 source "board/bachmann/ot1200/Kconfig"
 source "board/balloon3/Kconfig"
 source "board/barco/platinum/Kconfig"
diff --git a/board/hisilicon/hikey/Kconfig b/board/hisilicon/hikey/Kconfig
new file mode 100644
index 0000000..f7f1055
--- /dev/null
+++ b/board/hisilicon/hikey/Kconfig
@@ -0,0 +1,15 @@ 
+if TARGET_HIKEY
+
+config SYS_BOARD
+	default "hikey"
+
+config SYS_VENDOR
+	default "hisilicon"
+
+config SYS_SOC
+	default "hi6220"
+
+config SYS_CONFIG_NAME
+	default "hikey"
+
+endif
diff --git a/board/hisilicon/hikey/Makefile b/board/hisilicon/hikey/Makefile
new file mode 100644
index 0000000..d4ec8c7
--- /dev/null
+++ b/board/hisilicon/hikey/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= hikey.o
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
new file mode 100644
index 0000000..8c1271b
--- /dev/null
+++ b/board/hisilicon/hikey/hikey.c
@@ -0,0 +1,356 @@ 
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <usb.h>
+#include <power/hi6553_pmic.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/hi6220.h>
+
+/*TODO drop this table in favour of device tree */
+static const struct hikey_gpio_platdata hi6220_gpio[] = {
+	{ 0, HI6220_GPIO_BASE(0)},
+	{ 1, HI6220_GPIO_BASE(1)},
+	{ 2, HI6220_GPIO_BASE(2)},
+	{ 3, HI6220_GPIO_BASE(3)},
+	{ 4, HI6220_GPIO_BASE(4)},
+	{ 5, HI6220_GPIO_BASE(5)},
+	{ 6, HI6220_GPIO_BASE(6)},
+	{ 7, HI6220_GPIO_BASE(7)},
+	{ 8, HI6220_GPIO_BASE(8)},
+	{ 9, HI6220_GPIO_BASE(9)},
+	{ 10, HI6220_GPIO_BASE(10)},
+	{ 11, HI6220_GPIO_BASE(11)},
+	{ 12, HI6220_GPIO_BASE(12)},
+	{ 13, HI6220_GPIO_BASE(13)},
+	{ 14, HI6220_GPIO_BASE(14)},
+	{ 15, HI6220_GPIO_BASE(15)},
+	{ 16, HI6220_GPIO_BASE(16)},
+	{ 17, HI6220_GPIO_BASE(17)},
+	{ 18, HI6220_GPIO_BASE(18)},
+	{ 19, HI6220_GPIO_BASE(19)},
+
+};
+
+U_BOOT_DEVICES(hi6220_gpios) = {
+	{ "gpio_hi6220", &hi6220_gpio[0] },
+	{ "gpio_hi6220", &hi6220_gpio[1] },
+	{ "gpio_hi6220", &hi6220_gpio[2] },
+	{ "gpio_hi6220", &hi6220_gpio[3] },
+	{ "gpio_hi6220", &hi6220_gpio[4] },
+	{ "gpio_hi6220", &hi6220_gpio[5] },
+	{ "gpio_hi6220", &hi6220_gpio[6] },
+	{ "gpio_hi6220", &hi6220_gpio[7] },
+	{ "gpio_hi6220", &hi6220_gpio[8] },
+	{ "gpio_hi6220", &hi6220_gpio[9] },
+	{ "gpio_hi6220", &hi6220_gpio[10] },
+	{ "gpio_hi6220", &hi6220_gpio[11] },
+	{ "gpio_hi6220", &hi6220_gpio[12] },
+	{ "gpio_hi6220", &hi6220_gpio[13] },
+	{ "gpio_hi6220", &hi6220_gpio[14] },
+	{ "gpio_hi6220", &hi6220_gpio[15] },
+	{ "gpio_hi6220", &hi6220_gpio[16] },
+	{ "gpio_hi6220", &hi6220_gpio[17] },
+	{ "gpio_hi6220", &hi6220_gpio[18] },
+	{ "gpio_hi6220", &hi6220_gpio[19] },
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct peri_sc_periph_regs *peri_sc =
+	(struct peri_sc_periph_regs *)HI6220_PERI_BASE;
+
+struct alwayson_sc_regs *ao_sc =
+	(struct alwayson_sc_regs *)ALWAYSON_CTRL_BASE;
+
+/* status offset from enable reg */
+#define STAT_EN_OFF 0x2
+
+void hi6220_clk_enable(u32 bitfield, unsigned int *clk_base)
+{
+	uint32_t data;
+
+	data = readl(clk_base);
+	data |= bitfield;
+
+	writel(bitfield, clk_base);
+	do {
+		data = readl(clk_base + STAT_EN_OFF);
+	} while ((data & bitfield) == 0);
+}
+
+/* status offset from disable reg */
+#define STAT_DIS_OFF 0x1
+
+void hi6220_clk_disable(u32 bitfield, unsigned int *clk_base)
+{
+	uint32_t data;
+
+	data = readl(clk_base);
+	data |= bitfield;
+
+	writel(data, clk_base);
+	do {
+		data = readl(clk_base + STAT_DIS_OFF);
+	} while (data & bitfield);
+}
+
+#define EYE_PATTERN	0x70533483
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	unsigned int data;
+
+	/* enable USB clock */
+	hi6220_clk_enable(PERI_CLK0_USBOTG, &peri_sc->clk0_en);
+
+	/* take usb IPs out of reset */
+	writel(PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
+		PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K,
+		&peri_sc->rst0_dis);
+	do {
+		data = readl(&peri_sc->rst0_stat);
+		data &= PERI_RST0_USBOTG_BUS | PERI_RST0_POR_PICOPHY |
+			PERI_RST0_USBOTG | PERI_RST0_USBOTG_32K;
+	} while (data);
+
+	/*CTRL 5*/
+	data = readl(&peri_sc->ctrl5);
+	data &= ~PERI_CTRL5_PICOPHY_BC_MODE;
+	data |= PERI_CTRL5_USBOTG_RES_SEL | PERI_CTRL5_PICOPHY_ACAENB;
+	data |= 0x300;
+	writel(data, &peri_sc->ctrl5);
+
+	/*CTRL 4*/
+
+	/* configure USB PHY */
+	data = readl(&peri_sc->ctrl4);
+
+	/* make PHY out of low power mode */
+	data &= ~PERI_CTRL4_PICO_SIDDQ;
+	data &= ~PERI_CTRL4_PICO_OGDISABLE;
+	data |= PERI_CTRL4_PICO_VBUSVLDEXTSEL | PERI_CTRL4_PICO_VBUSVLDEXT;
+	writel(data, &peri_sc->ctrl4);
+
+	writel(EYE_PATTERN, &peri_sc->ctrl8);
+
+	mdelay(5);
+	return 0;
+}
+
+static int config_sd_carddetect(void)
+{
+	int ret;
+
+	/* configure GPIO8 as nopull */
+	writel(0, 0xf8001830);
+
+	gpio_request(8, "SD CD");
+
+	gpio_direction_input(8);
+	ret = gpio_get_value(8);
+
+	if (!ret) {
+		printf("%s: SD card present\n", __func__);
+		return 1;
+	}
+
+	printf("%s: SD card not present\n", __func__);
+	return 0;
+}
+
+
+static void mmc1_init_pll(void)
+{
+	uint32_t data;
+
+	/* select SYSPLL as the source of MMC1 */
+	/* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
+	writel(1 << 11 | 1 << 27, &peri_sc->clk0_sel);
+	do {
+		data = readl(&peri_sc->clk0_sel);
+	} while (!(data & (1 << 11)));
+
+	/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
+	writel(1 << 30, &peri_sc->clk0_sel);
+	do {
+		data = readl(&peri_sc->clk0_sel);
+	} while (data & (1 << 14));
+
+	hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
+
+	hi6220_clk_enable(PERI_CLK12_MMC1_SRC, &peri_sc->clk12_en);
+
+	do {
+		/* 1.2GHz / 50 = 24MHz */
+		writel(0x31 | (1 << 7), &peri_sc->clkcfg8bit2);
+		data = readl(&peri_sc->clkcfg8bit2);
+	} while ((data & 0x31) != 0x31);
+}
+
+static void mmc1_reset_clk(void)
+{
+	unsigned int data;
+
+	/* disable mmc1 bus clock */
+	hi6220_clk_disable(PERI_CLK0_MMC1, &peri_sc->clk0_dis);
+
+	/* enable mmc1 bus clock */
+	hi6220_clk_enable(PERI_CLK0_MMC1, &peri_sc->clk0_en);
+
+	/* reset mmc1 clock domain */
+	writel(PERI_RST0_MMC1, &peri_sc->rst0_en);
+
+	/* bypass mmc1 clock phase */
+	data = readl(&peri_sc->ctrl2);
+	data |= 3 << 2;
+	writel(data, &peri_sc->ctrl2);
+
+	/* disable low power */
+	data = readl(&peri_sc->ctrl13);
+	data |= 1 << 4;
+	writel(data, &peri_sc->ctrl13);
+	do {
+		data = readl(&peri_sc->rst0_stat);
+	} while (!(data & PERI_RST0_MMC1));
+
+	/* unreset mmc0 clock domain */
+	writel(PERI_RST0_MMC1, &peri_sc->rst0_dis);
+	do {
+		data = readl(&peri_sc->rst0_stat);
+	} while (data & PERI_RST0_MMC1);
+}
+
+/* PMU SSI is the IP that maps the external PMU hi6553 registers as IO */
+static void hi6220_pmussi_init(void)
+{
+	uint32_t data;
+
+	/* Take PMUSSI out of reset */
+	writel(ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N,
+	       &ao_sc->rst4_dis);
+	do {
+		data = readl(&ao_sc->rst4_stat);
+	} while (data & ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N);
+
+	/* set PMU SSI clock latency for read operation */
+	data = readl(&ao_sc->mcu_subsys_ctrl3);
+	data &= ~ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
+	data |= ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3;
+	writel(data, &ao_sc->mcu_subsys_ctrl3);
+
+	/* enable PMUSSI clock */
+	data = ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU |
+	       ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU;
+
+	hi6220_clk_enable(data, &ao_sc->clk5_en);
+
+	/* Output high to PMIC on PWR_HOLD_GPIO0_0 */
+	gpio_request(0, "PWR_HOLD_GPIO0_0");
+	gpio_direction_output(0, 1);
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->flags = 0;
+
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+
+static int init_dwmmc(void)
+{
+	int ret;
+
+#ifdef CONFIG_DWMMC
+
+	/* mmc0 clocks are already configured by ATF */
+	ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
+	if (ret)
+		printf("%s: Error configuring pinmux for eMMC (%d)\n"
+			, __func__, ret);
+
+	ret |= hi6220_dwmci_add_port(0, HI6220_MMC0_BASE, 8);
+	if (ret)
+		printf("%s: Error adding eMMC port (%d)\n", __func__, ret);
+
+
+	/* take mmc1 (sd slot) out of reset, configure clocks and pinmuxing */
+	mmc1_init_pll();
+	mmc1_reset_clk();
+
+	ret |= hi6220_pinmux_config(PERIPH_ID_SDMMC1);
+	if (ret)
+		printf("%s: Error configuring pinmux for eMMC (%d)\n"
+			, __func__, ret);
+
+	config_sd_carddetect();
+
+	ret |= hi6220_dwmci_add_port(1, HI6220_MMC1_BASE, 4);
+	if (ret)
+		printf("%s: Error adding SD port (%d)\n", __func__, ret);
+
+#endif
+	return ret;
+}
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+	/* init the hi6220 pmussi ip */
+	hi6220_pmussi_init();
+
+	power_hi6553_init((u8 *)HI6220_PMUSSI_BASE);
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	/* add the eMMC and sd ports */
+	ret = init_dwmmc();
+
+	if (ret)
+		debug("init_dwmmc failed\n");
+
+	return ret;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+/* Use the Watchdog to cause reset */
+void reset_cpu(ulong addr)
+{
+	/* TODO program the watchdog */
+}
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
new file mode 100644
index 0000000..aa4fb0d
--- /dev/null
+++ b/configs/hikey_defconfig
@@ -0,0 +1,5 @@ 
+# 96boards HiKey
+CONFIG_ARM=y
+CONFIG_TARGET_HIKEY=y
+CONFIG_NET=y
+# CONFIG_CMD_IMLS is not set
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
new file mode 100644
index 0000000..8ff9077
--- /dev/null
+++ b/include/configs/hikey.h
@@ -0,0 +1,159 @@ 
+/*
+ * (C) Copyright 2015 Linaro
+ *
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Configuration for HiKey 96boards CE. Parts were derived from other ARM
+ * configurations.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __HIKEY_H
+#define __HIKEY_H
+
+/* We use generic board for hikey */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_POWER
+#define CONFIG_POWER_HI6553
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* Cache Definitions */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_IDENT_STRING		"hikey"
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+/* Physical Memory Map */
+
+/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
+#define CONFIG_SYS_TEXT_BASE		0x35000000
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x00000000
+
+/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/
+#define PHYS_SDRAM_1_SIZE		0x3f000000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		19000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xf6801000
+#define GICC_BASE			0xf6802000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_SERIAL
+
+#define CONFIG_PL011_CLOCK		19200000
+#define CONFIG_PL01x_PORTS		{(void *)0xF8015000}
+#define CONFIG_CONS_INDEX		0
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000
+/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/
+#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MISC_INIT_R
+#endif
+
+#define CONFIG_HIKEY_GPIO
+#define CONFIG_DM_GPIO
+#define CONFIG_CMD_GPIO
+#define CONFIG_DM
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_DWMMC
+#define CONFIG_HIKEY_DWMMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_MMC
+
+#define CONFIG_FS_EXT4
+
+/* Command line configuration */
+#define CONFIG_MENU
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_UNZIP
+#define CONFIG_CMD_ENV
+
+#define CONFIG_MTD_PARTITIONS
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#include <config_distro_defaults.h>
+
+/* Initial environment variables */
+
+/*
+ * Defines where the kernel and FDT will be put in RAM
+ */
+
+/* Assume we boot with root on the seventh partition of eMMC */
+#define CONFIG_BOOTARGS	"console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 1) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+				"kernel_name=Image\0"	\
+				"kernel_addr_r=0x00080000\0" \
+				"fdt_name=hi6220-hikey.dtb\0" \
+				"fdt_addr_r=0x02000000\0" \
+				"fdt_high=0xffffffffffffffff\0" \
+				"initrd_high=0xffffffffffffffff\0" \
+				BOOTENV
+
+
+/* Preserve enviroment on sd card */
+#define CONFIG_COMMAND_HISTORY
+
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE               "mmc"
+#define FAT_ENV_DEVICE_AND_PART         "1:1"
+#define FAT_ENV_FILE                    "uboot.env"
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_NO_FLASH
+
+#endif /* __HIKEY_H */